stm32f10x_rcc.cpp

STM32 USB HID

#include"stm32f10x_flash.hpp"
//-----------------------------------------------------------------------------
#include"stm32f10x_rcc.hpp"
//-----------------------------------------------------------------------------
void RCC_Configration(void)	
{
	RCC_CR_BIT[HSE_ON]=1;
	while(!RCC_CR_BIT[HSE_RDY]);//Wait till HSE is ready

  // Enable Prefetch Buffer 
  {
		FLASH_ACR_BIT[LATENCY_2]=0;
		FLASH_ACR_BIT[LATENCY_1]=1;
		FLASH_ACR_BIT[LATENCY_0]=0;
	}
 
	/* HCLK = SYSCLK */
	{	//HCLK = SYSCLK 
		RCC_CFGR_BIT[HPRE_3]=0;
		RCC_CFGR_BIT[HPRE_2]=0;
		RCC_CFGR_BIT[HPRE_1]=0;
		RCC_CFGR_BIT[HPRE_0]=0;
	}
	/* PCLK2 = HCLK */
	{	//PCLK2 = HCLK
		RCC_CFGR_BIT[PPRE2_2]=0;
		RCC_CFGR_BIT[PPRE2_1]=0;
		RCC_CFGR_BIT[PPRE2_0]=0;
	}
	/* PCLK1 = HCLK/2 */
	{	//PCLK1 = HCLK/2
		RCC_CFGR_BIT[PPRE1_2]=1;
		RCC_CFGR_BIT[PPRE1_1]=0;
		RCC_CFGR_BIT[PPRE1_0]=0;
	}
	/* On STICE the PLL output clock is fixed to 72 MHz */
	RCC_CFGR_BIT[PLLSRC]=1;
	{	
		RCC_CFGR_BIT[PLLMUL_3]=0;
		RCC_CFGR_BIT[PLLMUL_2]=1;
		RCC_CFGR_BIT[PLLMUL_1]=1;
		RCC_CFGR_BIT[PLLMUL_0]=1;			
	}

	/* Enable PLL */ 
	RCC_CR_BIT[PLL_ON]=1;
	while(!RCC_CR_BIT[PLL_RDY]);//Wait till PLL is ready

	/* Select PLL as system clock source */
	{	//Select PLL as system clock source
		RCC_CFGR_BIT[SW_1]=1;
		RCC_CFGR_BIT[SW_0]=0;
	}	
	while(!RCC_CFGR_BIT[SWS_1]);//Wait till PLL is used as system clock source
}