stm32f10x_gp_timer.h

STM32 USB HID

#ifndef __STM32F10x_GP_TIMER_H__
#define __STM32F10x_GP_TIMER_H__
//-----------------------------------------------------------------------------
#define  TIMER2_CR1					(*((volatile unsigned long*)0x40000000))
#define  TIMER2_CR2					(*((volatile unsigned long*)0x40000004))
#define  TIMER2_SMCR				(*((volatile unsigned long*)0x40000008))
#define  TIMER2_DIER				(*((volatile unsigned long*)0x4000000C))
#define  TIMER2_SR	 				(*((volatile unsigned long*)0x40000010))
#define  TIMER2_EGR		 			(*((volatile unsigned long*)0x40000014))	
#define  TIMER2_CCMR1 			(*((volatile unsigned long*)0x40000018))
#define  TIMER2_CCMR2 			(*((volatile unsigned long*)0x4000001C))
#define  TIMER2_CCER 				(*((volatile unsigned long*)0x40000020))
#define  TIMER2_CNT					(*((volatile unsigned long*)0x40000024))
#define  TIMER2_PSC					(*((volatile unsigned long*)0x40000028))
#define  TIMER2_ARR					(*((volatile unsigned long*)0x4000002C))
#define  TIMER2_CCR1				(*((volatile unsigned long*)0x40000034))
#define  TIMER2_CCR2				(*((volatile unsigned long*)0x40000038))	 
#define  TIMER2_CCR3				(*((volatile unsigned long*)0x4000003C))
#define  TIMER2_CCR4				(*((volatile unsigned long*)0x40000040))
#define  TIMER2_DCR					(*((volatile unsigned long*)0x40000048))
#define  TIMER2_DMAR				(*((volatile unsigned long*)0x4000004C))
//-----------------------------------------------------------------------------
#define  TIMER2_CR1_BITS				((volatile unsigned long*)(0x42000000+(0x00000000<<5)))	
#define  TIMER2_CR2_BITS				((volatile unsigned long*)(0x42000000+(0x00000004<<5)))
#define  TIMER2_SMCR_BITS				((volatile unsigned long*)(0x42000000+(0x00000008<<5)))
#define  TIMER2_DIER_BITS				((volatile unsigned long*)(0x42000000+(0x0000000C<<5)))
#define  TIMER2_SR_BITS	 				((volatile unsigned long*)(0x42000000+(0x00000010<<5)))
#define  TIMER2_EGR_BITS		 		((volatile unsigned long*)(0x42000000+(0x00000014<<5)))	
#define  TIMER2_CCMR1_BITS 			((volatile unsigned long*)(0x42000000+(0x00000018<<5)))
#define  TIMER2_CCMR2_BITS 			((volatile unsigned long*)(0x42000000+(0x0000001C<<5)))
#define  TIMER2_CCER_BITS 			((volatile unsigned long*)(0x42000000+(0x00000020<<5)))
#define  TIMER2_CNT_BITS				((volatile unsigned long*)(0x42000000+(0x00000024<<5)))
#define  TIMER2_PSC_BITS				((volatile unsigned long*)(0x42000000+(0x00000028<<5)))
#define  TIMER2_ARR_BITS				((volatile unsigned long*)(0x42000000+(0x0000002C<<5)))
#define  TIMER2_CCR1_BITS				((volatile unsigned long*)(0x42000000+(0x00000034<<5)))
#define  TIMER2_CCR2_BITS				((volatile unsigned long*)(0x42000000+(0x00000038<<5)))	 
#define  TIMER2_CCR3_BITS				((volatile unsigned long*)(0x42000000+(0x0000003C<<5)))
#define  TIMER2_CCR4_BITS				((volatile unsigned long*)(0x42000000+(0x00000040<<5)))
#define  TIMER2_DCR_BITS				((volatile unsigned long*)(0x42000000+(0x00000048<<5)))
#define  TIMER2_DMAR_BITS				((volatile unsigned long*)(0x42000000+(0x0000004C<<5)))
//-----------------------------------------------------------------------------
#define  TIMER3_CR1					(*((volatile unsigned long*)0x40000400))
#define  TIMER3_CR2					(*((volatile unsigned long*)0x40000404))
#define  TIMER3_SMCR				(*((volatile unsigned long*)0x40000408))
#define  TIMER3_DIER				(*((volatile unsigned long*)0x4000040C))
#define  TIMER3_SR	 				(*((volatile unsigned long*)0x40000410))
#define  TIMER3_EGR		 			(*((volatile unsigned long*)0x40000414))	
#define  TIMER3_CCMR1 			(*((volatile unsigned long*)0x40000418))
#define  TIMER3_CCMR2 			(*((volatile unsigned long*)0x4000041C))
#define  TIMER3_CCER 				(*((volatile unsigned long*)0x40000420))
#define  TIMER3_CNT					(*((volatile unsigned long*)0x40000424))
#define  TIMER3_PSC					(*((volatile unsigned long*)0x40000428))
#define  TIMER3_ARR					(*((volatile unsigned long*)0x4000042C))
#define  TIMER3_CCR1				(*((volatile unsigned long*)0x40000434))
#define  TIMER3_CCR2				(*((volatile unsigned long*)0x40000438))	 
#define  TIMER3_CCR3				(*((volatile unsigned long*)0x4000043C))
#define  TIMER3_CCR4				(*((volatile unsigned long*)0x40000440))
#define  TIMER3_DCR					(*((volatile unsigned long*)0x40000448))
#define  TIMER3_DMAR				(*((volatile unsigned long*)0x4000044C))
//-----------------------------------------------------------------------------
#define  TIMER3_CR1_BITS				((volatile unsigned long*)(0x42000000+(0x00000400<<5)))	
#define  TIMER3_CR2_BITS				((volatile unsigned long*)(0x42000000+(0x00000404<<5)))
#define  TIMER3_SMCR_BITS				((volatile unsigned long*)(0x42000000+(0x00000408<<5)))
#define  TIMER3_DIER_BITS				((volatile unsigned long*)(0x42000000+(0x0000040C<<5)))
#define  TIMER3_SR_BITS	 				((volatile unsigned long*)(0x42000000+(0x00000410<<5)))
#define  TIMER3_EGR_BITS		 		((volatile unsigned long*)(0x42000000+(0x00000414<<5)))	
#define  TIMER3_CCMR1_BITS 			((volatile unsigned long*)(0x42000000+(0x00000418<<5)))
#define  TIMER3_CCMR2_BITS 			((volatile unsigned long*)(0x42000000+(0x0000041C<<5)))
#define  TIMER3_CCER_BITS 			((volatile unsigned long*)(0x42000000+(0x00000420<<5)))
#define  TIMER3_CNT_BITS				((volatile unsigned long*)(0x42000000+(0x00000424<<5)))
#define  TIMER3_PSC_BITS				((volatile unsigned long*)(0x42000000+(0x00000428<<5)))
#define  TIMER3_ARR_BITS				((volatile unsigned long*)(0x42000000+(0x0000042C<<5)))
#define  TIMER3_CCR1_BITS				((volatile unsigned long*)(0x42000000+(0x00000434<<5)))
#define  TIMER3_CCR2_BITS				((volatile unsigned long*)(0x42000000+(0x00000438<<5)))	 
#define  TIMER3_CCR3_BITS				((volatile unsigned long*)(0x42000000+(0x0000043C<<5)))
#define  TIMER3_CCR4_BITS				((volatile unsigned long*)(0x42000000+(0x00000440<<5)))
#define  TIMER3_DCR_BITS				((volatile unsigned long*)(0x42000000+(0x00000448<<5)))
#define  TIMER3_DMAR_BITS				((volatile unsigned long*)(0x42000000+(0x0000044C<<5)))
//CR1--------------------------------------------------------------------------
#define ARPE  7
#define OPM   3
#define CEN   0
//EGR--------------------------------------------------------------------------
#define UG   0
//CCMR1------------------------------------------------------------------------
#define CC2S_1 9
#define CC2S_0 8

#define OC1M_2 6
#define OC1M_1 5
#define OC1M_0 4

#define CC1S_1 1
#define CC1S_0 0
//CCMR2------------------------------------------------------------------------
#define CC2S_1 9
#define CC2S_0 8

#define OC3M_2 6
#define OC3M_1 5
#define OC3M_0 4

#define CC1S_1 1
#define CC1S_0 0
//CCER-------------------------------------------------------------------------
#define CC3P  9
#define CC3E  8
#define CC2P  5
#define CC1P  1
#define CC1E  0
//-----------------------------------------------------------------------------
#endif