lpc11xx.h

LPC11C14 CAN 代码

/*
 *  end of group LPC11xx_SSP
 *  @}
 */

/*********************************************************************************************************
  Inter-Integrated Circuit (I2C)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface 
 *  @{
 */
typedef struct
{
    __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W)             */
    __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ )                  */
    __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W)                    */
    __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W)         */
    __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word(R/W)*/
    __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W)*/
    __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W)           */
    __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W)        */
    __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W)         */
    __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W)         */
    __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W)         */
    __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W)                 */
    __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W)    */
    __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W)    */
    __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W)    */
    __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W)    */
} LPC_I2C_TypeDef;
/*
 *  end of group LPC11xx_I2C
 *  @}
 */

/*********************************************************************************************************
  Watchdog Timer (WDT)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer 
 *  @{
 */
typedef struct
{
    __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W)               */
    __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W)     */
    __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register ( /W)      */
    __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R/ )        */
         uint32_t RESERVED0;
    __IO uint32_t WARNINT;
    __IO uint32_t WINDOW;
} LPC_WDT_TypeDef;
/*
 *  end of group LPC11xx_WDT
 *  @}
 */

/*********************************************************************************************************
  Analog-to-Digital Converter (ADC)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter 
 *  @{
 */
typedef struct
{
    __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W)           */
    __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W)       */
         uint32_t RESERVED0;
    __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W)  */
    __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
    __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ )            */
} LPC_ADC_TypeDef;
/*
 *  end of group LPC11xx_ADC
 *  @}
 */

/*********************************************************************************************************
  CAN Controller (CAN)
*********************************************************************************************************/
/*
 *  @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) 
 *  @{
 */
typedef struct
{
    __IO uint32_t CNTL;                                                 /* 0x000                        */
    __IO uint32_t STAT;
    __IO uint32_t EC;
    __IO uint32_t BT;
    __IO uint32_t INT;
    __IO uint32_t TEST;
    __IO uint32_t BRPE;
         uint32_t RESERVED0;
    __IO uint32_t IF1_CMDREQ;                                           /* 0x020                        */
    __IO uint32_t IF1_CMDMSK;
    __IO uint32_t IF1_MSK1;
    __IO uint32_t IF1_MSK2;
    __IO uint32_t IF1_ARB1;
    __IO uint32_t IF1_ARB2;
    __IO uint32_t IF1_MCTRL;
    __IO uint32_t IF1_DA1;
    __IO uint32_t IF1_DA2;
    __IO uint32_t IF1_DB1;
    __IO uint32_t IF1_DB2;
         uint32_t RESERVED1[13];   
    __IO uint32_t IF2_CMDREQ;                                           /* 0x080                        */
    __IO uint32_t IF2_CMDMSK;
    __IO uint32_t IF2_MSK1;
    __IO uint32_t IF2_MSK2;
    __IO uint32_t IF2_ARB1;
    __IO uint32_t IF2_ARB2;
    __IO uint32_t IF2_MCTRL;
    __IO uint32_t IF2_DA1;
    __IO uint32_t IF2_DA2;
    __IO uint32_t IF2_DB1;
    __IO uint32_t IF2_DB2;
         uint32_t RESERVED2[21];
    __I  uint32_t TXREQ1;                                               /* 0x100                        */
    __I  uint32_t TXREQ2;
         uint32_t RESERVED3[6];
    __I  uint32_t ND1;                                                  /* 0x120                        */
    __I  uint32_t ND2;
         uint32_t RESERVED4[6];
    __I  uint32_t IR1;                                                  /* 0x140                        */
    __I  uint32_t IR2;
         uint32_t RESERVED5[6];
    __I  uint32_t MSGV1;                                                /* 0x160                        */
    __I  uint32_t MSGV2;
         uint32_t RESERVED6[6];
    __IO uint32_t CLKDIV;                                               /* 0x180                        */
} LPC_CAN_TypeDef;
/*
 *  end of group LPC11xx_CAN
 *  @}
 */

#if defined ( __CC_ARM   )
#pragma no_anon_unions
#endif


/*********************************************************************************************************
  ----------------------------------------Peripheral memory map------------------------------------------
*********************************************************************************************************/
/*
 *  Base addresses
 */
#define LPC_FLASH_BASE        (0x00000000UL)
#define LPC_RAM_BASE          (0x10000000UL)
#define LPC_APB0_BASE         (0x40000000UL)
#define LPC_AHB_BASE          (0x50000000UL)

/*
 *  APB0 peripherals
 */
#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)
#define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)
#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)
#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)
#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)
#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)
#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
#define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
#define LPC_CAN_BASE          (LPC_APB0_BASE + 0x50000)
#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)

/*
 *  AHB peripherals
 */
#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)

/*********************************************************************************************************
  ----------------------------------------Peripheral declaration ----------------------------------------
*********************************************************************************************************/
#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
#define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )
#define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )
#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
#define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )
#define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )
#define LPC_CAN               ((LPC_CAN_TypeDef    *) LPC_CAN_BASE   )
#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )

#ifdef __cplusplus
}
#endif

#endif                                                                  /* __LPC11xx_H__                */

/*********************************************************************************************************
  End Of File
*********************************************************************************************************/