core_cm0.h

LPC11C14 CAN 代码

/*********************************************************************************************************
** @brief  Return the Control Register value 
**
** @param  none
** @return uint32_t Control value
**
** Return the content of the control register
*********************************************************************************************************/
extern uint32_t __get_CONTROL(void);

/*********************************************************************************************************
** @brief  Set the Control Register value
**
** @param  uint32_t Control value
** @return none
**
** Set the control register
*********************************************************************************************************/
extern void __set_CONTROL(uint32_t control);

/*********************************************************************************************************
** @brief  Reverse byte order in integer value
**
** @param  uint32_t value to reverse
** @return uint32_t reversed value
**
** Reverse byte order in integer value
*********************************************************************************************************/
extern uint32_t __REV(uint32_t value);

/*********************************************************************************************************
** @brief  Reverse byte order in unsigned short value
**
** @param  uint16_t value to reverse
** @return uint32_t reversed value
**
** Reverse byte order in unsigned short value
*********************************************************************************************************/
extern uint32_t __REV16(uint16_t value);

/*********************************************************************************************************
** Reverse byte order in signed short value with sign extension to integer
**
** @param  int16_t value to reverse
** @return int32_t reversed value
**
** @brief  Reverse byte order in signed short value with sign extension to integer
*********************************************************************************************************/
extern int32_t __REVSH(int16_t value);

/*
 *  TASKING Compiler
 */
#elif (defined (__TASKING__))

/*
 *  TASKING carm specific functions
 */
/*********************************************************************************************************
** The CMSIS functions have been implemented as intrinsics in the compiler.
** Please use "carm -?i" to get an up to date list of all instrinsics,
** Including the CMSIS ones.
*********************************************************************************************************/

#endif


/*********************************************************************************************************
  NVIC functions
*********************************************************************************************************/

/*
 *  Interrupt Priorities are WORD accessible only under ARMv6M
 *  The following MACROS handle generation of the register offset and byte masks
 */
#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )


/*********************************************************************************************************
** @brief  Enable Interrupt in NVIC Interrupt Controller
**
** @param  IRQn_Type IRQn specifies the interrupt number
** @return none 
**
** Enable a device specific interupt in the NVIC interrupt controller.
** The interrupt number cannot be a negative value.
*********************************************************************************************************/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));   /* enable interrupt                             */
}

/*********************************************************************************************************
** @brief  Disable the interrupt line for external interrupt specified
** 
** @param  IRQn_Type IRQn is the positive number of the external interrupt
** @return none
** 
** Disable a device specific interupt in the NVIC interrupt controller.
** The interrupt number cannot be a negative value.
*********************************************************************************************************/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));   /* disable interrupt                            */
}

/*********************************************************************************************************
** @brief  Read the interrupt pending bit for a device specific interrupt source
** 
** @param  IRQn_Type  IRQn is the number of the device specifc interrupt
** @return uint32_t   1 if pending interrupt else 0
**
** Read the pending register in NVIC and return 1 if its status is pending, 
** otherwise it returns 0
*********************************************************************************************************/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
                                                        /* Return 1 if pending else 0                   */
}

/*********************************************************************************************************
** @brief  Set the pending bit for an external interrupt
** 
** @param  IRQn_Type IRQn is the Number of the interrupt
** @return none
**
** Set the pending bit for the specified interrupt.
** The interrupt number cannot be a negative value.
*********************************************************************************************************/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));   /* set interrupt pending                        */
}

/*********************************************************************************************************
** @brief  Clear the pending bit for an external interrupt
**
** @param  IRQn_Type  IRQn is the Number of the interrupt
** @return none
**
** Clear the pending bit for the specified interrupt. 
** The interrupt number cannot be a negative value.
*********************************************************************************************************/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));   /* Clear pending interrupt                      */
}

/*********************************************************************************************************
** @brief  Set the priority for an interrupt
**
** @param  IRQn_Type  IRQn is the Number of the interrupt
** @param  uint32_t   priority is the priority for the interrupt
** @return none
**
** Set the priority for the specified interrupt. The interrupt 
** number can be positive to specify an external (device specific) 
** interrupt, or negative to specify an internal (core) interrupt. \n
**
** Note: The priority cannot be set for every core interrupt.
*********************************************************************************************************/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
    if(IRQn < 0) {
        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
    else {
        NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}

/*********************************************************************************************************
** @brief  Read the priority for an interrupt
**
** @param  IRQn_Type IRQn is the Number of the interrupt
** @return priority is the priority for the interrupt
**
** Read the priority for the specified interrupt. The interrupt 
** number can be positive to specify an external (device specific) 
** interrupt, or negative to specify an internal (core) interrupt.
**
** The returned priority value is automatically aligned to the implemented
** priority bits of the microcontroller.
**
** Note: The priority cannot be set for every core interrupt.
*********************************************************************************************************/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
    if(IRQn < 0) {
        return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  }
                                                        /* get priority for Cortex-M0 system interrupts */
    else {
        return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  }
                                                        /* get priority for device specific interrupts  */
}


/*********************************************************************************************************
  SysTick function
*********************************************************************************************************/

#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)

/*
 *  SysTick constants
 */
#define SYSTICK_ENABLE              0                 /* Config-Bit to start or stop the SysTick Timer  */
#define SYSTICK_TICKINT             1                 /* Config-Bit to enable or disable the SysTick    */
                                                      /* interrupt                                      */
#define SYSTICK_CLKSOURCE           2                 /* Clocksource has the offset 2 in SysTick Control*/
                                                      /* and Status Register                            */
#define SYSTICK_MAXCOUNT       ((1<<24) -1)           /* SysTick MaxCount                               */

/*********************************************************************************************************
** @brief  Initialize and start the SysTick counter and its interrupt.
**
** @param  uint32_t ticks is the number of ticks between two interrupts
** @return  none
**
** Initialise the system tick timer and its interrupt and start the
** system tick timer / counter in free running mode to generate 
** periodical interrupts.
*********************************************************************************************************/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
    if (ticks > SYSTICK_MAXCOUNT)  return (1);                  /* Reload value impossible              */

    SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;           /* set reload register                  */
    NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System    */
                                                                /* Interrupts                           */
    SysTick->VAL   =  (0x00);                                   /* Load the SysTick Counter Value       */
    SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); 
                                                                /* Enable SysTick IRQ and SysTick Timer */
    return (0);                                                 /* Function successful                  */
}

#endif


/*********************************************************************************************************
  Reset function
*********************************************************************************************************/

/*********************************************************************************************************
** @brief  Initiate a system reset request.
**
** @param   none
** @return  none
**
** Initialize a system reset request to reset the MCU
*********************************************************************************************************/
static __INLINE void NVIC_SystemReset(void)
{
    SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (1<<NVIC_SYSRESETREQ));   /* Keep priority group unchanged      */
    __DSB();                                                      /* Ensure completion of memory access */
    while(1);                                                     /* wait until reset                   */
}


#ifdef __cplusplus
}
#endif

#endif                                                            /* __CM0_CORE_H__                     */


/*********************************************************************************************************
  End Of File
*********************************************************************************************************/