为随机马及crc实现.txt

这是一个编码器的实现的程序

library ieee;
use ieee.std_logic_1164.all;
entity crc is
port(clk,reset:in std_logic;
       q:out std_logic;
       q1:out std_logic_vector(15 downto 0));
end crc;
architecture crc_arch of crc is
signal dout:std_logic_vector(3 downto 0);
begin
process(clk,reset)
variable t:std_logic;
begin
t:=dout(0) xor dout(3);
if clk'event and clk='1'then
if reset='1'then
dout<="1010";
elsif reset='0' then
dout<=t&dout(3 downto 1);
end if;
end if;
q<=dout(0);
end process;
process(clk,reset)
variable t1,t2,t3:std_logic;
variable d_new:std_logic_vector(15 downto 0);
begin
t1:=d_new(0) xor dout(0);
t2:=d_new(11) xor '1';
t3:=d_new(4) xor '1';
if clk'event and clk='0'then
if reset='1'then
d_new:="0000000000000000";
elsif t1='1'then
d_new:=t1&d_new(15 downto 12)&t2&d_new(10 downto 5)&t3&d_new(3 downto 1);
elsif t1='0'then
d_new:=t1&d_new(15 downto 1);
end if;
end if;
q1<=d_new;
end process;
end crc_arch;