📄 crc-8串行输入.txt
字号:
library ieee;
use ieee.std_logic_1164.all;
entity crc is
port(clk,s_in,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end crc;
architecture crc_arch of crc is
signal t1,t2,t3:std_logic;
signal d_new:std_logic_vector(7 downto 0);
begin
t1<=d_new(0) xor s_in;
t2<=d_new(4) xor '1';
t3<=d_new(3) xor '1';
process(clk,reset)
begin
if clk'event and clk='1'then
if reset='1'then
d_new<="00000000";
elsif t1='1'then
d_new<=t1&d_new(7 downto 5)&t2&t3&d_new(2 downto 1);
elsif t1='0'then
d_new<=t1&d_new(7 downto 1);
end if;
end if;
end process;
q<=d_new;
end crc_arch;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -