代装载的移位寄存器.txt

这是一个编码器的实现的程序

process(clk,load)
variable REG16:std_logic_vector(15 downto 0);
begin
if clk'event and clk='1'then
if load='1' then 
REG16:=d_new;
else 
REG16(14 downto 0):=REG16(15 downto 1);
end if;
end if;
end process;
q_crc<=dout(0) when sel='0' else REG16(0);