📄 crc-16快速实现程序.txt
字号:
library ieee;
use ieee. std_logic_1164. all;
entity PLI_CRC is
port (
PLI: in std_logic_vector (15 downto 0) ;
Chec: out std_logic_vector (15 downto 0)
) ;
end PLI_CRC;
architecture art of PLI_CRC is
type mem is array ( 0 to 15) of std_logic_vector
(15 downto 0) ;
signal ramtmp: mem;
begin
ramtmp(0)<= "0001000000100001" ;
ramtmp(1)<= "0010000001000010" ;
ramtmp(2)<= "0100000010000100" ;
ramtmp(3)<= "1000000100001000" ;
ramtmp(4)<= "0001001000110001" ;
ramtmp(5)<= "0010010001100010" ;
ramtmp(6)<= "0100100011000100" ;
ramtmp(7)<= "1001000110001000" ;
ramtmp(8)<= "0011001100110001" ;
ramtmp(9)<= "0110011001100010" ;
ramtmp(10)<= "1100110011000100" ;
ramtmp(11)<= "1000100110101001" ;
ramtmp(12)<= "0000001101110011" ;
ramtmp(13)<= "0000011011100110" ;
ramtmp(14)<= "0000110111001100" ;
ramtmp(15)<= "0001101110011000" ;
process(PLI)
variable crc_tmp: std_logic_vector ( 15 downto
0) ;
begin
crc_tmp:="0000000000000000" ;
for i in 0 to 15 loop
if PLI(i)='1' then
crc_tmp:=crc_tmp xor ramtmp ( i) ;
end if;
end loop;
Chec<=crc_tmp;
end process;
end art;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -