时钟控制.txt

来自「这是一个编码器的实现的程序」· 文本 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aa is
port(clk,reset:in std_logic;
     load,sel:out std_logic);
end aa;
architecture B of aa is
begin
process(clk,reset)
variable count:std_logic_vector(4 downto 0);
begin
if clk'event and clk='1'then
if reset='1' then
count:="000000";
elsif count=31 then
count:="000000";
else
count:=count+1;
end if;
if count=16 then
load<='1';
else
load<='0';
end if;
if count>=0 and count<16 then
sel<='0';
else
sel<='1';
end if;
end if;
end process;
end B;