board.h

MPC850的bootrom。使用后可以直接启动boot程序

/* board.h - GTT100 board header */

/* Copyright 2002 GTT, Inc. */

/*
modification history
--------------------

*/

/*
This file contains I/O addresses and related constants for the GTT100. 
*/

#ifndef	_BOARD_H
#define	_BOARD_H

#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"

#define BUS	0				/* bus-less board */
#define CPU	PPC860				/* CPU type */

#define N_SIO_CHANNELS	 	1		/* No. serial I/O channels */

/*************************************** gtt *********************************************
*                                  CS CONFIGURATION                                       
*  some register parameters which need to be changed according to the different boards   
*    *CS0                          - bootrom, 8-bit port size;   
*    *CS1                          - SDRAM,16-bit port size;                            
*    *CS2                          - DOC, 8-bit port size;                            
*    *CS3                          - FLASH, 16-bit port size;   
******************************************************************************************/
#define BR0_VAL                        0x08000401      /* define bootrom base address */
#define OR0_VAL                        0xfff80962      /* define bootrom size  512KB*/

#define BR1_VAL                        0x00000881      /* define sdram base address */
#define OR1_VAL                        0xff800a00      /* define sdram size  8MB*/

#define BR2_VAL                        0x0C000401      /* 0x0E000401->0x0C000401  2004.11.24 */
#define OR2_VAL                        0xffff0962      /* Define DOC size  8KB*/

#define BR3_VAL                        0x0A000801      /* define flash base address */
#define OR3_VAL                        0xff800942      /* define flash size  8MB*/

#define BR4_VAL                        0x0E000401      /* Define DOC base address */
#define OR4_VAL                        0xffff0962      /* Define DOC size  8KB*/

#define BR5_VAL                        0x0E100401      /* Define DOC base address */
#define OR5_VAL                        0xffff0962      /* Define DOC size  8KB*/

#define BR6_VAL                        0x0E200401      /* Define DOC base address */
#define OR6_VAL                        0xffff0962      /* Define DOC size  8KB*/

#define BR7_VAL                        0x0E300401      /* Define DOC base address */
#define OR7_VAL                        0xffff0962      /* Define DOC size  8KB*/


/*************************************** gtt *********************************************
*    BASIC   ADDRESS  PARAMTER                                          
*                        
*    *ROM_BASE_ADRS_VAL             - bootrom base address;                              
*    *RAM_HIGH_ADRS_VAL             - RAM address for ROM boot                           
*    *RAM_LOW_ADRS_VAL              - RAM address for sys image                          
*    *FLASH_ADRS                    - RAM address for ROM boot                           
*    *LOCAL_MEM_LOCAL_ADRS_VAL      - Base of RAM                                        
*    *UPDPRAM_ADDR                  - Base address of UP DPRAM                            
*    *DNDPRAM_ADDR                  - Base address of DOWN DPRAM                            
******************************************************************************************/
#define RAM_HIGH_ADRS_VAL           0x00200000               /*for boot program*/
#define RAM_LOW_ADRS_VAL            0x00010000               /*for vxworks image*/
#define USER_RESERVED_MEM_VAL       0x00000000
#define ROM_BASE_ADRS_VAL           (BR0_VAL&0xffff8000)
#define LOCAL_MEM_LOCAL_ADRS_VAL    (BR1_VAL&0xffff8000)
#define DOC_ADDR                    (BR2_VAL&0xffff8000) 
#define FLASH_ADDR                  (BR3_VAL&0xffff8000)

#define CS4_ADDR                  (BR4_VAL&0xffff8000)
#define CS5_ADDR                  (BR5_VAL&0xffff8000)
#define CS6_ADDR                  (BR6_VAL&0xffff8000)
#define CS7_ADDR                  (BR7_VAL&0xffff8000)


 
/*************************************** gtt *********************************************
*                                  SIZE CONFIGURATION                                      
*    *ROM_SIZE                     - ROM space ;                                          
*    *SDRAM_SIZE                   - the size of sdram  ;                                
*    *FLASH_SIZE                   - FLASH size ;   
******************************************************************************************/ 
#undef  ROM_SIZE
#define ROM_SIZE              0x00080000 	             /* 512k ROM space */
#undef  SDRAM_SIZE
#define SDRAM_SIZE            0x00800000               /* 8MB */
#undef  FLASH_SIZE
#define FLASH_SIZE           	0x01000000               /* 16MB */

#define DOC_SIZE              0x2000                   /* 8KB */


/*************************************** gtt **********************************************
*                         SDRAM PARAMETER                                                
*                                                                                        
*  some parameters are used when initializing the  sdram                                 
*    *SDRAM_REFRESH_FREQ         - sdram refresh freq;                                   
*    *MPTPR_VAL                  - Periodic timers prescaler;                            
*    *MCR1                       - Issue precharge command;                              
*    *MCR2                       - run refresh pattern 8 times;                          
*    *MCR3                       - Run MRS pattern;                                      
******************************************************************************************/
#define SDRAM_REFRESH_FREQ	            64000		/* 64 Khz */
#define MPTPR_VAL                      0x2000
/*#define MAMR_VAL                       0xC3820111 */
/*#define MAMR_VAL                       0xC3800114
#define MCR1_VAL                       0x80002105       Issue precharge command */
#define MAMR_VAL                       0xBB820114       /*BB,AMX = 00 A10 - A12*/ 
#define MCR1_VAL                       0x80002106       /*Issue precharge command */
#define MCR2_VAL                       0x80002830       /*run refresh pattern 8 times*/
/*#define MCR3_VAL                       0x80002106       Run MRS pattern 
#define MAR_VAL                        0x48 */
#define MCR3_VAL                       0x80002138       /*Run MRS pattern */
/*#define MAR_VAL                        0x46*/
#define MAR_VAL                        0x46

#define FREQ_20_MHZ		20000000	/* 20 Mhz */
#define FREQ_24_MHZ  24000000 /* 24 Mhz */
#define FREQ_25_MHZ		25000000	/* 25 Mhz */
#define FREQ_48_MHZ  48000000 /* 48 Mhz */
#define FREQ_50_MHZ		50000000	/* 50 Mhz */


#define	PC_BASE_ADRS_0		0x02000000	/* PCMCIA base address */
#define	PC_SIZE_0		0x00100000	/* PCMCIA mapping size */
#define	PC_BASE_ADRS_1		0x04000000	/* PCMCIA base address */
#define	PC_SIZE_1		0x02000000	/* PCMCIA mapping size */

/* 
 * SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register.
 * PLPRCR is set by sysHwInit() in sysLib.c. 
 * SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h
 */

#define SPLL_MUL_FACTOR	((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)


/*
 * SPLL Frequency - gives the SPLL real frequency divide by 2
 */

#define SPLL_FREQ	((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)   /* SPLL_FREQ = 50MHz  gtt  */
                  

/*
 * Baud Rate Generator Clock - gives the Baud Rate Generator Clock (BRGCLK)
 * Frequency. 
 */

#define BRGCLK_FREQ	(SPLL_FREQ / ( 1 << (2 * BRGCLK_DIV_FACTOR)))

/* 
 * Refresh value - defines the number of BRGCLK period between two 
 * DRAM refresh cycle.
 */

/* #define REFRESH_VALUE	(BRGCLK_FREQ / DRAM_REFRESH_FREQ) gtt  */

/* 
 * Periodic Timer A period - value used to set the PTA bits of
 * the Machine A Mode Register (MAMR). This register is used to
 * controle the User_Programmable Machine A (UPM). The UPM is part of
 * the memory controller.
 */

/*#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \
			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \
			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \
			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \
			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \
			  (REFRESH_VALUE /  2))))))*/


/* 
 * Periodic Timer Prescaler Division Factor - gives the division factor
 * of the Periodic Timer Prescaler (PTP). The PTP is part of the 
 * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the
 * Periodic Timer. 
 * This macro is used to set the DRAM refresh cycle period.
 */

/*#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)*/
#define PTP_DIV_FACTOR	 4    /*MPTPR = 0X1000  gtt */

/*
 * PTP Value - translate the Periodic Timer Prescaler Division Factor 
 * to the value to place in the PTP register.
 */

#define PTP_VALUE	( PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \
			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \
			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \
			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \
			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \
			  MPTPR_PTP_DIV64)))))

#define TMBCLK_FREQ	 (CRISTAL_FREQ/16)  /* SCCR[TBS]=0, MODCK[1-2] = 10, MF+1=1, 故TMB=OSCCLK/16  gtt */   

/* define the decrementer input clock frequency */
#define DEC_CLOCK_FREQ	TMBCLK_FREQ

#define DEC_CLK_TO_INC  1

/* define system clock rate */
#define	SYS_CPU_FREQ	SPLL_FREQ

/* Internal Memory Map base Address */
#define INTERNAL_MEM_MAP_ADDR		0xFF000000   /*IMMR 0x02200000-->0xFF000000  by gtt 2.20*/
#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes */

/* size of the on-board SDRAM */
#define SDRAM_SIZE			0x00800000	  /* 4 Meg --> 8 Meg  gtt*/
#define SDRAM_REFRESH_FREQ		64000		/* 64 Khz */

/* CPU type in the PVR */
#define CPU_TYPE_860			0x0050		/* value for PPC860 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */

/* Ethernet parameters */

#ifdef  INCLUDE_CPM				/* CPM ethernet driver */

#define INCLUDE_IF_USR
#define IF_USR_NAME     "cpm"                   /* device name */
#define IF_USR_ATTACH   sysCpmAttach            /* driver attach routine */
						/* address of SCC param RAM */
#define IF_USR_ARG1     (char *) INTERNAL_MEM_MAP_ADDR + 0x3c00 
#define IF_USR_823ARG1  (char *) INTERNAL_MEM_MAP_ADDR + 0x3d00 
						/* address of SCC regs */
#define IF_USR_ARG2     (int)INTERNAL_MEM_MAP_ADDR + 0x0a00    
#define IF_USR_823ARG2  (int)INTERNAL_MEM_MAP_ADDR + 0x0a20

#define IF_USR_ARG3     (int) IV_SCC1           /* int number for SCC1 */
#define IF_USR_823ARG3  (int) IV_SCC2           /* int number for SCC2 */
						/* address of transmit BDs */
#define IF_USR_ARG4     (int) INTERNAL_MEM_MAP_ADDR + 0x2000
						/* address of receive BDs */
#define IF_USR_ARG5     (int) INTERNAL_MEM_MAP_ADDR + 0x2100
#define IF_USR_ARG6     (int) 0x20              /* number of transmit BDs */
#define IF_USR_ARG7     (int) 0x20              /* number of receive BDs */
#define IF_USR_ARG8     (int) NONE              /* allocate mem for buffers */

#endif  /* INCLUDE_CPM */


#endif /* _BOARD_H */