syssccserial.c

MPC850的bootrom。使用后可以直接启动boot程序

/* sysSerial.c -  MPC860 SCC UART BSP serial device initialization */

/* Copyright 1984-1998 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01a,25may01,wmj  created
*/

/*
The sysSccSerial.c file is normally included as part of the sysLib.c file.
This code segment configures the serial ports for the BSP.
This BSP can support up to three SCC channels in UART mode only.
*/
 
#include "vxWorks.h"
#include "iv.h"
#include "intLib.h"
#include "config.h"
#include "sysLib.h"
#include "drv/sio/ppc860Sio.h"
#include "drv/multi/ppc860Cpm.h"
#include "board.h"

/* defines */

/* 
 * the macros below define parameters describing the configuration of
 * the SCCs channels in the PPC860's DPRAM, for instance the offset
 * of the transmit buffer descriptors (TBD), receive buffer descriptors
 * (RBD), and so on. The user may redefine them to best suit its needs.
 * He should be aware of the location of other peripherals's parameters
 * within the DPRAM (SCC1, etc.).
 */

/* offset from DPRAM of SCC3's TBDs */

/*#define SCC3_TBD_OFF		0x600*/
#define SCC3_TBD_OFF		0x800

/* offset from DPRAM of SCC3's RBDs */

#define SCC3_RBD_OFF		(SCC3_TBD_OFF + 0x10)

/* offset from DPRAM of SCC3's Tx buffers */

/*#define SCC3_TX_BUF_OFF		0x700*/
#define SCC3_TX_BUF_OFF		0x900

/* size of the SCC3 transmit buffer */

#define SCC3_TX_BUF_SZ		0x01

/* offset from DPRAM of SCC3's Rx buffers */

#define SCC3_RX_BUF_OFF		(SCC3_TX_BUF_OFF + 0x80)

/* number of SCC3's TBDs */

#define SCC3_TBD_NUM		0x01

/* number of SCC3's RBDs */

#define SCC3_RBD_NUM		0x10


/* offset from DPRAM of SCC4's TBDs */

/*#define SCC4_TBD_OFF		0x800*/
#define SCC4_TBD_OFF		0xa00

/* offset from DPRAM of SCC4's RBDs */

#define SCC4_RBD_OFF		(SCC4_TBD_OFF + 0x10)

/* offset from DPRAM of SCC4's Tx buffers */

/*#define SCC4_TX_BUF_OFF		0x900*/
#define SCC4_TX_BUF_OFF		0xb00

/* size of the SCC4 transmit buffer */

#define SCC4_TX_BUF_SZ		0x01

/* offset from DPRAM of SCC4's Rx buffers */

#define SCC4_RX_BUF_OFF		(SCC4_TX_BUF_OFF + 0x80)

/* number of SCC4's TBDs */

#define SCC4_TBD_NUM		0x01

/* number of SCC4's RBDs */

#define SCC4_RBD_NUM		0x10

/* device initialization structure */
 
typedef struct
    {
    UINT32	sccTbdOff;		/* offset of the TBDs for this scc */
    UINT32	sccRbdOff;		/* offset of the RBDs for this scc */
    UINT32	sccTbdNum;		/* number of TBDs for this scc */
    UINT32	sccRbdNum;		/* number of RBDs for this scc */
    UINT32	sccTxBufOff;		/* offset of the Tx buf for this scc */
    UINT32	sccRxBufOff;		/* offset of the Rx buf for this scc */
    UINT32	sccTxBufSz;		/* size of the Tx buf for this scc */
    } PPC860SCC_PARMS;
 
/* forward declaration */

/* Local data structures */
 
static UINT8	sccChanNum = SCC_TTY_NUM;	/* number of channels actually used */

/*static int SCC_NUM[] = {3,4};		 usage SCC3, and SCC4 */
static int SCC_NUM[] = {3};			/* usage SCC3, and SCC4 */

/*
static PPC860SCC_PARMS ppc860SccParms [] =
    {
	   {SCC3_TBD_OFF, SCC3_RBD_OFF, SCC3_TBD_NUM, SCC3_RBD_NUM,
		SCC3_TX_BUF_OFF, SCC3_RX_BUF_OFF, SCC3_TX_BUF_SZ},
		
	   {SCC4_TBD_OFF, SCC4_RBD_OFF, SCC4_TBD_NUM, SCC4_RBD_NUM,
		SCC4_TX_BUF_OFF, SCC4_RX_BUF_OFF, SCC4_TX_BUF_SZ},
    };
*/
 static PPC860SCC_PARMS ppc860SccParms [] =
    {
	   {SCC3_TBD_OFF, SCC3_RBD_OFF, SCC3_TBD_NUM, SCC3_RBD_NUM,
		SCC3_TX_BUF_OFF, SCC3_RX_BUF_OFF, SCC3_TX_BUF_SZ},
    };
static PPC860SCC_CHAN	ppc860SccChan [SCC_TTY_NUM];

/******************************************************************************
*
* sysSerialHwInit - initialize the BSP serial devices to a quiesent state
*
* This routine initializes the BSP serial device descriptors and puts the
* devices in a quiesent state.  It is called from sysHwInit() with
* interrupts locked.
*
* Both the SCC serial channels are initialized if the variable sccChanNum 
* equals two. In this case, SCC1 uses BRG1 and SCC2 uses BRG2. However, 
* if using an MPC823/850 processor, only SCC1 is initialized.
*
* Data Parameter Ram layout:
*
*          -----------------------------
*          |                           | DPRAM base 
*          |                           |
*          |                           |
*          |                           |
*          |---------------------------|
*          | 8 bytes per descriptor       | SCC1 Tx Buffer Descriptor (0x2200)
*          |---------------------------|
*          |                           |
*          |---------------------------|
*          | 16 descriptors @            | SCC1 Rx Buffer Descriptors (0x2210)
*          | 8 bytes per descriptor    | 
*          |                           |
*          |---------------------------|
*          |                           | end SCC1 Rx BDs (0x2290)
*          |                           |
*          |                           |
*          |---------------------------|
*          | 80 bytes allowed          | SCC1 Tx Buffer (0x2300 + DPRAM base )
*          |---------------------------|
*          | one receive char/buffer   | SCC1 Rx Buffer (0x2380 + DPRAM base )
*          |---------------------------|
*          |                           |
*          |                           |
*          |---------------------------|
*          | 8 bytes per descriptor    | SCC2 Tx Buffer Descriptor (0x2400)
*          |---------------------------|
*          |                           |
*          |---------------------------|
*          | 16 descriptors @          | SCC2 Rx Buffer Descriptors (0x2410)
*          | 8 bytes per descriptor    | 
*          |                           |
*          |---------------------------|
*          |                           | end SCC2 Rx BDs (0x2490)
*          |                           |
*          |                           |
*          |---------------------------|
*          | 80 bytes allowed          | SCC2 Tx Buffer (0x2500 + DPRAM base )
*          |---------------------------|
*          | one receive char/buffer   | SCC2 Rx Buffer (0x2580 + DPRAM base )
*          |---------------------------|
*          |                           |
*          |                           |
*          |---------------------------|
*          | 8 bytes per descriptor    | SCC3 Tx Buffer Descriptor (0x2600)
*          |---------------------------|
*          |                           |
*          |---------------------------|
*          | 16 descriptors @          | SCC3 Rx Buffer Descriptors (0x2610)
*          | 8 bytes per descriptor    | 
*          |                           |
*          |---------------------------|
*          |                           | end SCC3 Rx BDs (0x2690)
*          |                           |
*          |                           |
*          |---------------------------|
*          | 80 bytes allowed          | SCC3 Tx Buffer (0x2700 + DPRAM base )
*          |---------------------------|
*          | one receive char/buffer   | SCC3 Rx Buffer (0x2780 + DPRAM base )
*          |---------------------------|
*          |                           |
*          |                           |
*          |                           |
*          |                           |
*          |---------------------------|
*          | 128 bytes of parameter info| SCC1 Parameter Area (0x3c00)
*          | including Rx and Tx BD    | 
*          | pointers, func codes      |
*          | etc...                    |
*          |---------------------------|
*          |                           |
*          |---------------------------|
*          | 128 bytes of parameter info| SCC2 Parameter Area (0x3d00)
*          | including Rx and Tx BD    | 
*          | pointers, func codes      |
*          | etc...                    |
*          |---------------------------|
*          |                           |
*          |---------------------------|
*          | 128 bytes of parameter info| SCC3 Parameter Area (0x3e00)
*          | including Rx and Tx BD    | 
*          | pointers, func codes      |
*          | etc...                    |
*          |---------------------------|
*          |                           |
*          |                           |
*
*
*
* RETURNS: N/A
*/ 

int sysSccSerialHwInit (void)
    {
    int		i;		/* an index */
	int 	j,n;
	int		*ptrl;	
	
	if(sizeof(SCC_NUM)/sizeof(int) != sccChanNum)	
		return(ERROR);
			
    /* intialize the chips device descriptors */

   for (i = 0; i < sccChanNum; i++) 
  /* for (i = (SCC_NUM[0]-1); i < (SCC_NUM[0]-1+sccChanNum); i++) */
    {
		UINT32 regBase;

		/* BRGCLK freq (Hz) */

		ppc860SccChan[i].clockRate = BRGCLK_FREQ;	    

		/* IMMR reg has base adr */

		ppc860SccChan[i].regBase = vxImmrGet();  	    

		regBase = ppc860SccChan[i].regBase;

		/* use BRG1 for channel 1, BRG2 for channel 2 and  BRG3 for channel 3 */

		ppc860SccChan[i].bgrNum = (i + 1);                  

		/* SCC wired for rs232 */

		if(SCC_NUM[i] <1 || SCC_NUM[i] >4)	return(ERROR);
		
		ppc860SccChan[i].uart.sccNum = SCC_NUM[i];                  

		/* init the number of TBDs */

		ppc860SccChan[i].uart.txBdNum = ppc860SccParms[i].sccTbdNum;                  

		/* init the number of RBDs */

		ppc860SccChan[i].uart.rxBdNum = ppc860SccParms[i].sccRbdNum;               

		/* transmit BD base adrs */

		ppc860SccChan[i].uart.txBdBase = (SCC_BUF *) 
						 (MPC860_REGB_OFFSET + 
						 ppc860SccParms[i].sccTbdOff);

		/* receive BD base adrs */

		ppc860SccChan[i].uart.rxBdBase  = (SCC_BUF *) 
						 (MPC860_REGB_OFFSET + 
						 ppc860SccParms[i].sccRbdOff);

		/* tx buf base */

		ppc860SccChan[i].uart.txBufBase = (u_char *) 
						 (MPC860_DPRAM_BASE (regBase)
						 + ppc860SccParms[i].sccTxBufOff);
		/* rx buf base */

		ppc860SccChan[i].uart.rxBufBase = (u_char *) 
						 (MPC860_DPRAM_BASE (regBase)
						 + ppc860SccParms[i].sccRxBufOff);

		/* transmit buffer size */

		ppc860SccChan[i].uart.txBufSize = ppc860SccParms[i].sccTxBufSz;

		/* Clear DPRAM value before using. */
		ptrl = (int *)(ppc860SccChan[i].uart.txBdBase);
		n = ppc860SccChan[i].uart.txBdNum * 2;
		for(j=0; j<n; j++)	*(ptrl + j) = 0;
				
		ptrl = (int *)(ppc860SccChan[i].uart.rxBdBase);
		n = ppc860SccChan[i].uart.rxBdNum * 2;
		for(j=0; j<n; j++)	*(ptrl + j) = 0;

		ptrl = (int *)(ppc860SccChan[i].uart.txBufBase);
		n = 0x20;
		for(j=0; j<n; j++)	*(ptrl + j) = 0;

		ptrl = (int *)(ppc860SccChan[i].uart.rxBufBase);
		n = 0x20;
		for(j=0; j<n; j++)	*(ptrl + j) = 0;


		/* DPRAM addr of SCCx params */

		ppc860SccChan[i].uart.pScc = (SCC *) ((UINT32) PPC860_DPR_SCC1 
						    (MPC860_DPRAM_BASE (regBase)) 
						    + ((ppc860SccChan[i].uart.sccNum - 1) * 0x100));

		/* GSMR for SCCx */

		ppc860SccChan[i].uart.pSccReg = (SCC_REG *) 
					       ((UINT32) MPC860_GSMR_L1 (regBase)
					       + ((ppc860SccChan[i].uart.sccNum - 1) * 0x20));

		/* Mask interrupts */

		ppc860SccChan[i].uart.pSccReg->sccm = 0;              

		ppc860SccChan[i].pBaud = (UINT32 *) ((UINT32) MPC860_BRGC1 (regBase)
						    + (i * 4));
		ppc860SccChan[i].channelMode = 0;

		/* select RS232 pins */
		/* You must update the next lines according to you system. */
		switch(ppc860SccChan[i].uart.sccNum)
		{
			case 1:		/* SCC1, TXD1--PA[14],  RXD1--PA[15]*/
				*MPC860_PAPAR(regBase) |= 0x0003;	
				*MPC860_PADIR(regBase) &= ~(0x0003);
				break;
				
			case 2:		/* SCC2,  TXD1--PA[12],  RXD1--PA[13] */
				*MPC860_PAPAR(regBase) |= 0x000C;	
				*MPC860_PADIR(regBase) &= ~(0x000C);
				break;
				
			case 3:		/* SCC3 TXD1--PD[10],  RXD1--PD[11] */
/*				*MPC860_PDPAR(regBase) |= 0x0030;
				*MPC860_PDDIR(regBase) &= ~(0x0030);
		*/
			/*	*MPC860_PAPAR(regBase) |= 0x00C0;	*/ /*  PA9--SMRXD2   PA8--SMTXD2*/
			/*	*MPC860_PADIR(regBase) &= ~(0x00C0); */
			*MPC860_PBPAR(regBase) |= 0x0006;
			*MPC860_PBDIR(regBase) &= ~(0x0006);
				break;
				
			case 4:		/* SCC4 TXD1--PD[8],  RXD1--PD[9] */
				*MPC860_PDPAR(regBase) |= 0x00c0;
				*MPC860_PDDIR(regBase) &= ~(0x00c0);
				break;
				
			default:
				return(ERROR);
		}

		/* set it to normal operations */

		*MPC860_SDCR(regBase) = SDCR_RAID_BR5;           

		/* reset the chip */

		ppc860SccDevInit(&(ppc860SccChan [i]));
    }
	return(OK);
}

/******************************************************************************
*
* sysSerialHwInit2 - connect BSP serial device interrupts
*
* This routine connects the BSP serial device interrupts.  It is called from
* sysHwInit2().  Serial device interrupts could not be connected in
* sysSerialHwInit() because the kernel memory allocator was not initialized
* at that point, and intConnect() calls malloc().
*
* RETURNS: N/A
*/ 

void sysSccSerialHwInit2 (void)
    {
    int		i;	/* an index */

    /* connect serial interrupts */

    for (i = 0; i < sccChanNum; i++)
	{
	switch (SCC_NUM[i])
	    {
	    case 1:
			(void) intConnect (IV_SCC1, (VOIDFUNCPTR) ppc860SccInt, 
					   (int) &ppc860SccChan[i]);
			break;

	    case 2:
			(void) intConnect (IV_SCC2, (VOIDFUNCPTR) ppc860SccInt, 
					   (int) &ppc860SccChan[i]);
			break;

	    case 3:
			(void) intConnect (IV_SCC3, (VOIDFUNCPTR) ppc860SccInt, 
					   (int) &ppc860SccChan[i]);
			break;

	    case 4:
			(void) intConnect (IV_SCC4, (VOIDFUNCPTR) ppc860SccInt, 
					   (int) &ppc860SccChan[i]);
			break;

	    default:
			return;
	    }

	*CIMR(vxImmrGet()) |= (CIMR_SCC1 >> i);
	}
    }

/******************************************************************************
*
* sysSccSerialChanGet - get the SIO_CHAN device associated with a serial channel
*
* This routine gets the SIO_CHAN device associated with a specified serial
* channel.
*
* RETURNS: A pointer to the SIO_CHAN structure for the channel, or ERROR
* if the channel is invalid.
*/

SIO_CHAN * sysSccSerialChanGet
    (
    int channel		/* serial channel */
    )
    {
    if (channel >= sccChanNum)
		return ((SIO_CHAN *) ERROR);

    return ((SIO_CHAN *) &ppc860SccChan[channel]);
    }

/*******************************************************************************
*
* sysSerialReset - reset the serail device 
*
* This function calls sysSerialHwInit() to reset the serail device
*
* RETURNS: N/A
*
*/

void sysSccSerialReset (void)
    {
    	sysSccSerialHwInit ();
    }