rominit.s

MPC850的bootrom。使用后可以直接启动boot程序

   sth   r5, MPTPR(0)(r4)  /* modified by gtt  */
    
#ifdef INCLUDE_SDRAM
   /*----------------------------------------------------------------------
    program UPM tables by writing to its 16 RAM locations. Note that 
    initialization of UPM RAM must be done before the Base Register
    initialization for SDRAM. Otherwise, system will hang when refresh
    starts.
   -----------------------------------------------------------------------*/

   /*
   * load r6/r7 with the start/end address of the UPM table for an
   * SDRAM @ 50MHZ.
   */

   lis     r6, HIADJ(upmaTableSdram)
   addi    r6, r6, LO(upmaTableSdram)
   lis     r7, HIADJ(upmaTableSdramEnd)
   addi    r7, r7, LO(upmaTableSdramEnd)

   /* init UPMB for memory access */

   sub     r5,r7,r6            /* Get total of bytes */
   srawi   r5,r5,2             /* divide by 4 to get actual of entries */
   
   /* convert UpmTable to ROM based addressing */
 
   lis     r7, HIADJ(romInit)
   addi    r7, r7, LO(romInit)
 
   lis     r8, HIADJ(ROM_TEXT_ADRS)
   addi    r8, r8, LO(ROM_TEXT_ADRS)
 
   sub     r6, r6, r7              /* subtract romInit base address */
   add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */

   lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
   addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)

   /*--------------------------------------------------
    Transfer the data from code memory to UPM memory
   --------------------------------------------------*/

UpmWriteLoop:

   lwz        r10,0(r6)              /* get data from table */
   stw        r10,MDR(0)(r4)         /* store the data to MD register */
  
   stw        r9,MCR(0)(r4)          /* issue command to MCR register */

   addi       r6,r6,4               /* next entry in the table */
   addi       r9,r9,1               /* next MAD address */
   
   addi       r5,r5,-1
   cmpwi      r5,0
   bne        UpmWriteLoop

   lis     r5, HIADJ(MAMR_VAL)
   addi    r5, r5, LO(MAMR_VAL)          
   stw     r5, MAMR(0)(r4)             /* gtt  */
 
   /*------------------
     start sdram init:
   ------------------*/
/* precharg all banks */
   lis     r5, HIADJ(MCR1_VAL)
   addi    r5, r5, LO(MCR1_VAL)   /* MCR = 0x80002105 */
   stw     r5, MCR(0)(r4)
              
/* refresh 8 times */   
   lis     r5, HIADJ(MCR2_VAL)
   addi    r5, r5, LO(MCR2_VAL)   /* MCR = 0x80002830 */
   stw     r5, MCR(0)(r4)

/* set mode register  burst lengh = 4 ; addressing mode = sequential ;cas lattency = 2 ; burst r/w */
   lis     r5, HIADJ(MAR_VAL)
   addi    r5, r5, LO(MAR_VAL)         /* MAR = 0x48 */
   stw     r5, MAR(0)(r4)

   lis     r5, HIADJ(MCR3_VAL)
   addi    r5, r5, LO(MCR3_VAL)   /* MCR = 0x80002114 */        
   stw     r5, MCR(0)(r4)        

   /* program OR1 and BR1 for 8 Mbytes SDRAM Memory Array  gtt */ 
   lis     r5, HIADJ(BR1_VAL)   
   addi    r5, r5, LO(BR1_VAL)
   stw     r5, BR1(0)(r4)    

   lis     r5, HIADJ(OR1_VAL)    
   ori     r5, r5, LO(OR1_VAL)  
   stw     r5, OR1(0)(r4)   
                
        
/* testing SDRAM */
   /*bl mem_check  */   /* gtt */
   
#endif /* INCLUDE_SDRAM */
  
 
   /* initialize the stack pointer */
   lis     sp, HIADJ(STACK_ADRS)
   addi    sp, sp, LO(STACK_ADRS)

   /* go to C entry point */

   addi sp, sp, -FRAMEBASESZ  /* get frame stack */

 /* 
  * calculate C entry point: routine - entry point + ROM base 
  * routine = romStart
  * entry point = romInit = R7
  * ROM base = ROM_TEXT_ADRS = R8
  * C entry point: romStart - R7 + R8 
  */
   
   lis     r7, HIADJ(romInit)
   addi    r7, r7, LO(romInit)
 
   lis     r8, HIADJ(ROM_TEXT_ADRS)
   addi    r8, r8, LO(ROM_TEXT_ADRS)

   lis     r6, HIADJ(romStart) 
   addi    r6, r6, LO(romStart) /* load R6 with C entry point */

   sub     r6, r6, r7  /* routine - entry point */
   add     r6, r6, r8   /* + ROM base */

   mtlr    r6   /* move C entry point to LR */
   blr          /* jump to the C entry point */


/* This 50 MHz SDRAM table is for...
 *   860EN Rev B.1 9829 and newer silicon
 *   860T  Rev B.3 9832 and newer silicon
 *
 */
 
upmaTableSdram:
 
 /*-----------------
 UPM A contents:
  -----------------*/
 
/*----------------------------------------------------
 * Read Single Beat Cycle. Offset 0 in the RAM array.
 *----------------------------------------------------
 */
 .long    0x1f07fc04,  0xeeaefc04,  0x11adfc04, 0xefbbbc00  
 .long    0x1ff77c47,  0xffffffff,  0x0ff33c04,  0xfffffc67 

/*------------------------------------------------
 * Read Burst Cycle. Offset 0x8 in the RAM array.
 *------------------------------------------------
 */
 .long    0x1f07fc04,  0xeeaefc04,  0x10adfc04,  0xf0affc00
 .long    0xf0affc00,  0xf0affc00,  0xf0affc00,  0xf0affc00
 .long    0xf0affc00,  0xf1affc00,  0xefbbbc00,  0x1ff77c47 
 .long    0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff 

/*-------------------------------------------------------
 * Write Single Beat Cycle. Offset 0x18 in the RAM array
 *-------------------------------------------------------
 */
 .long    0x1f27fc04,  0xeeaebc00,  0x01b93c04,  0x1ff77c47  
 .long    0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff 

/*-------------------------------------------------
 * Write Burst Cycle. Offset 0x20 in the RAM array
 *-------------------------------------------------
 */
 .long    0x1f07fc04,  0xeeaebc00,  0x10ad7c00,  0xf0affc00  
 .long    0xf0affc00,  0xf0affc00,  0xf0affc40,  0xf0affc00  
 .long    0xf0affc00,  0xe1bbbc04,  0x1ff77c47,  0xffffffff  
 .long    0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff 

/*------------------------------------------------------------------------
 * Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
 *------------------------------------------------------------------------
 */
 .long    0x1ff5fc84,  0xfffffc04,  0xfffffc04,  0xfffffc04 
 .long    0xfffffc84,  0xfffffc07,  0xffffffff,  0xffffffff
 .long    0x0ffffc34,  0x0f003c00,  0xfffffc67,  0xffffffff
/*-----------
 * Exception:
 *-----------
 */ 
 .long    0x7ffffc07,  0xffffffff,  0xffffffff,  0xffffffff 
    
  
upmaTableSdramEnd:


/* check 16M BYTE memory */
mem_check:

   mfspr    r30,LR    

   addis    r11,0,0x0905
   ori      r11,r11,0x0905    

test_ram:

   addis    r3,0,0x0080      /* ram size = 8M */
   addis    r5,0,0x0000      /* RAM start address */
   addis    r8,0,0

write_ram:
   stw      r8,0(r5)
   addi     r5,r5,4
   add      r8,r8,r11        
   cmpw     r5,r3
   bne      write_ram


   addis    r5,0,0x0000      /* RAM start address */
   addis    r8,0,0

read_ram:
   lwz      r10,0(r5)
   cmpw     r10,r8
   bne      mem_error
   addi     r5,r5,4
   add      r8,r8,r11
   cmpw     r5,r3
   bne      read_ram

   b        mem_ok

mem_error:
   bl       flash_error
   b        mem_error

mem_ok:
   bl       flash_ok
   bl       flash_ok
   bl       flash_ok
   
   addis    r11,r11,0x0007
   ori      r11,r11,0x0007

   mtspr    LR,r30      /* restore original Link Register value */

   bclr     20,0        /* jump unconditionally to effective address in Link */
                   

flash_ok:

   mfspr    r29,LR        

flash_run:

   addi     r8, 0, 0xfffe
   stw      r8,PCDAT(0)(r4)   /* 点亮RUN灯 */ 

   addis    r3,0,0x0000
   ori      r3,r3,0x7F08
   
delay_run_on:
   subi    r3,r3,1
   cmpwi   r3,0
   bne     delay_run_on
 
   addi     r8, 0, 0xffff     
   stw      r8,PCDAT(0)(r4)   /* 熄灭RUN灯 */    


   addis    r3,0,0x0000
   ori      r3,r3,0x07F08

delay_run_off:
   subi    r3,r3,1
   cmpwi   r3,0
   bne     delay_run_off

   mtspr    LR,r29      

   bclr     20,0        
   
   
flash_error:

   mfspr    r29,LR        

   addi     r8, 0, 0xfffe   
   stw      r8,PCDAT(0)(r4)  /* 点亮RED灯 */ 

   addis    r3,0,0x0000
   ori      r3,r3,0x7F08

delay_error_on:
   subi    r3,r3,1
   cmpwi   r3,0
   bne     delay_error_on
 
   addi     r8, 0, 0xffff      
   stw      r8,PCDAT(0)(r4)   /* 熄灭RED灯 */
 
 
   addis    r3,0,0x0000
   ori      r3,r3,0x7F08

delay_error_off:
   subi    r3,r3,1
   cmpwi   r3,0
   bne     delay_error_off

   mtspr    LR,r29     

   bclr     20,0