rominit.s

MPC850的bootrom。使用后可以直接启动boot程序

/* romInit.s - GTT100 board ROM initialization module */

/* Copyright 1984-1996 Wind River Systems, Inc. */
 .data
 .globl  copyright_wind_river
 .long   copyright_wind_river

/*
modification history
--------------------
2004.3.10   gtt  modified for GTT100
01a,19apr96,tpr  written.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h" 
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
 

 /* internals */

 .globl _romInit /* start of system code */
 .globl romInit  /* start of system code */
 
 /* externals */

 .extern romStart /* system initialization routine */
 
 .text
 .align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType /@ only used by 2nd entry point @/
*     )

*/
   .space (0x100)    /* gtt  */    

_romInit:
romInit:
 bl cold  /* jump to the cold boot initialization */
 
 bl start  /* jump to the warm boot initialization */

 /* copyright notice appears at beginning of ROM (in TEXT segment) */

 .ascii   "Copyright 1984-1996 Wind River Systems, Inc."
 .align 2

cold:
 li r3, BOOT_COLD /* set cold boot as start type */

 /*
  * When the PowerPC 860 is powered on, the processor fletch the
  * instructions located at the address 0x100. We need to jump
  * from the address 0x100 to the Flash space.
  */

 lis     r4, HIADJ(start)  /* load r4 with the address */
 addi    r4, r4, LO(start)  /* of start */

 lis     r5, HIADJ(romInit)  /* load r5 with the address */
 addi    r5, r5, LO(romInit)  /* of romInit() */

 lis     r6, HIADJ(ROM_TEXT_ADRS) /* load r6 with the address */
 addi    r6, r6, LO(ROM_TEXT_ADRS) /* of ROM_TEXT_ADRS */

 sub     r4, r4, r5   
 add     r4, r4, r6 

 mtspr   LR, r4    /* save destination address*/
                   /* into LR register */
 blr     /* jump to flash mem address */
   
start: /* 此处是系统启动开始 */
/* 屏蔽MSR(cpu状态寄存器)中CE,EE位,关闭所有的外部中断，它可以被读出通过指令mfmsr，mtmsr，sc，rlf

 /* set the MSR register to a known state */

 xor     r4, r4, r4  /* clear register R4 */
 addi    r4, r4, 0x0002
 mtmsr   r4       /* clear the MSR register */

 /* DER - clear the Debug Enable Register */

 mtspr DER, r4

 /* ICR - clear the Interrupt Cause Register */

 mtspr ICR, r4

 /* 
  * ICTRL - initialize the Intstruction Support Control register
  *    
  */

 lis     r5, HIADJ(0x00000007)
 addi    r5, r5, LO(0x00000007)
 mtspr   ICTRL, r5

 /* disable the instruction/data cache */
 
 lis     r4, HIADJ ( CACHE_CMD_DISABLE)  /* load disable cmd */
 addi    r4, r4, LO (CACHE_CMD_DISABLE)
 mtspr   IC_CST, r4                /* disable I cache */
 mtspr   DC_CST, r4                /* disable D cache */

 /* unlock the instruction/data cache */

 lis     r4, HIADJ ( CACHE_CMD_UNLOCK_ALL) /* load unlock cmd */
 addi    r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
 mtspr   IC_CST, r4                   /* unlock all I cache lines */
 mtspr   DC_CST, r4                   /* unlock all D cache lines */

 /* invalidate the instruction/data cache */

 lis     r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/
 addi    r4, r4, LO (CACHE_CMD_INVALIDATE)
 mtspr   IC_CST, r4  /* invalidate all I cache lines */
 mtspr   DC_CST, r4  /* invalidate all D cache lines */

 /*turn on I_cache*/
 lis     r4, HIADJ ( CACHE_CMD_ENABLE) 
 addi    r4, r4, LO (CACHE_CMD_ENABLE)
 mtspr   IC_CST, r4                /* enable I cache */
 
/* mfspr	r4, IC_CST
 isync
 sync
 ori	r4, r4, 0x02000000  	
 mtspr   IC_CST, r4           */     /* enable I cache */
 
 

 /*
  * initialize the IMMR register before any non-core registers
  * modification.
  */

 lis     r4, HIADJ(INTERNAL_MEM_MAP_ADDR) 
 addi    r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
 mtspr   IMMR, r4      /* initialize the IMMR register */

 mfspr   r4, IMMR         /* read it back, to be sure */
 rlwinm  r4, r4, 0, 0, 15 /* only high 16 bits count */

/* PB15=1 PB14=0 */
/*
 lis     r5, HIADJ (0x00030000)
 addi    r5, r5, LO(0x00030000)
 stw     r5, PBDIR(r4)    
 
 addis    r5,0, 0xFFFD
 ori      r5,r5,0xFFFF     
 stw      r5,PBDAT(0)(r4)
*/

 addi     r5, 0, 0x0003
 sth      r5, PCDIR(0)(r4)   /* PC15  output */

 addi     r5, 0, 0xfffc
 sth      r5, PCDAT(0)(r4)   /* PC15=0, 点亮RUN灯 */

 /* SYPCR - turn off the system protection stuff */
 
 lis     r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 addi    r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 stw     r5, SYPCR(0)(r4)   /* SYPCR = 0XFFFFFF88  gtt  */

 /*
  * Map the bank 0 to the flashROM area - On the GTT100 board at reset time
  * the bank 0 is already used to map the flash.
  */
   lis     r5, HIADJ(BR0_VAL)   
   addi    r5, r5, LO(BR0_VAL)
   stw     r5, BR0(0)(r4)     /* BR0 = 0x08000401  gtt  */

   lis     r5, HIADJ(OR0_VAL)    
   ori     r5, r5, LO(OR0_VAL)  
   stw     r5, OR0(0)(r4)     /* OR0 = 0xFFF80962  gtt */
 
 /*
  * Map the bank 2 to the DOC area
  
   lis     r5, HIADJ(BR2_VAL)   
   addi    r5, r5, LO(BR2_VAL)
   stw     r5, BR2(0)(r4)    

   lis     r5, HIADJ(OR2_VAL)    
   ori     r5, r5, LO(OR2_VAL)  
   stw     r5, OR2(0)(r4)       
 */
 
 /*
  * Map the bank 3 to the FLASH area
  */
   lis     r5, HIADJ(BR3_VAL)   
   addi    r5, r5, LO(BR3_VAL)
   stw     r5, BR3(0)(r4)    

   lis     r5, HIADJ(OR3_VAL)    
   ori     r5, r5, LO(OR3_VAL)  
   stw     r5, OR3(0)(r4)           

#if 0

 /*
  * Map the bank 4 to the FLASH area
  */
   lis     r5, HIADJ(BR4_VAL)   
   addi    r5, r5, LO(BR4_VAL)
   stw     r5, BR4(0)(r4)    

   lis     r5, HIADJ(OR4_VAL)    
   ori     r5, r5, LO(OR4_VAL)  
   stw     r5, OR4(0)(r4)  

 /*
  * Map the bank 5 to the FLASH area
  */
   lis     r5, HIADJ(BR5_VAL)   
   addi    r5, r5, LO(BR5_VAL)
   stw     r5, BR5(0)(r4)    

   lis     r5, HIADJ(OR5_VAL)    
   ori     r5, r5, LO(OR5_VAL)  
   stw     r5, OR5(0)(r4)  
   
    /*
  * Map the bank 6 to the FLASH area
  */
   lis     r5, HIADJ(BR6_VAL)   
   addi    r5, r5, LO(BR6_VAL)
   stw     r5, BR6(0)(r4)    

   lis     r5, HIADJ(OR6_VAL)    
   ori     r5, r5, LO(OR6_VAL)  
   stw     r5, OR6(0)(r4)  
    /*
  * Map the bank 7 to the FLASH area
  */
   lis     r5, HIADJ(BR7_VAL)   
   addi    r5, r5, LO(BR7_VAL)
   stw     r5, BR7(0)(r4)    

   lis     r5, HIADJ(OR7_VAL)    
   ori     r5, r5, LO(OR7_VAL)  
   stw     r5, OR7(0)(r4)  
#endif

 /* set the SIUMCR register for important debug port, etc... stuff */
 
   lis   r6, HIADJ(SIUMCR_DLK | SIUMCR_FRC)
   addi  r6, r6, LO(SIUMCR_DLK | SIUMCR_FRC)
   lwz   r5, SIUMCR(0)(r4)
   or    r5, r5, r6
   stw   r5, SIUMCR(0)(r4)
 /*   
   lis   r6, HIADJ( SIUMCR_DLK  | SIUMCR_DPC | SIUMCR_MLRC_3STATES )
   addi  r6, r6, LO(SIUMCR_DLK  | SIUMCR_DPC | SIUMCR_MLRC_3STATES )
   lwz   r5, SIUMCR(0)(r4)
   or    r5, r5, r6
   stw   r5, SIUMCR(0)(r4)
 */  
 /* TBSCR - initialize the Time Base Status and Control register */

   lis   r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
   addi  r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
   sth   r5, TBSCR(0)(r4)

 /* set PIT status and control init value */

   li    r5, PISCR_PS | PISCR_PITF
   sth   r5, PISCR(0)(r4)

 /* set the SPLL frequency */
   lis   r5, HIADJ(PLPRCR_TEXPS)
   addi  r5, r5, LO(PLPRCR_TEXPS)
   stw   r5, PLPRCR(0)(r4)

 /* 
  * we program the MPTPR with the largest allowed divider 
  * and the PTA value accordingly. So here we figure out the 
  * correct value for the PTA field.
  */
   addi  r5, 0, MPTPR_VAL