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MPC850的bootrom。使用后可以直接启动boot程序

                 README: Motorola MPC821/860ADS &  MPC8xxFADS

This file contains board-specific information for the Motorola MPC821/860ADS
and MPC8xxFADS target boards.  Specifically, this file contains information
on any BSP interface changes from previous software or hardware versions, and
contains caveats that the user must be aware of before using this BSP.
Additionally, the target board's manual page entry (i.e., man ads860)
provides board-specific information necessary to run VxWorks, and
should be read before this BSP is used.
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RELEASE 1.2/0

	First release for Tornado 2.0.

FCS RELEASE 1.1/4, Feb 1998 Tornado 1.0.1
        Added support for the MPC860T daughter boards and the Fast
        Ethernet Controller (FEC). Turned off data cache when the
        MPC860T is used. See also the relevant documentation in target.nr 
        in the bsp directory under "SPECIAL CONSIDERATIION" for more 
        information on this release's support to the FEC.

	Also fixed the following SPRs:
 
	SPR# 20049 There may be interrupt nesting trouble in Ppc860Intr.c
	SPR# 9451  ppc860Siu.h contains errors that cause system crashes
	SPR# 24337 The ads860 does not support SDRAM
	SPR# 23387 config.h is missing the definition of NV_RAM_SIZE
	SPR# 22572 ROM_SIZE in config.h does not match that for Makefile
	SPR# 24296 Missing comment in ppc860Sio.h
	SPR# 22503 DPRAM defines for SMC and PIP are missing a parenthesis
	SPR# 24295 Qualifier volatile needed in if_cpm.h and ppc860Cpm.h
	SPR# 20337 In the ppc860Cpm.h file, some definitions are wrong
	SPR# 22321 problems in ppc860Intr.c
	SPR# 21252 The timestamp driver is not working
	SPR# 20751 target.txt no longer updated
	SPR# 10005 The second on-board serial port is not initialized.
	SPR# 9946  ldppc warning: cannot find entry symbol _usrInit 
	SPR# 9351  spy is not supported
	SPR# 9220  vxWorks.st_rom does not boot, DEFAULT_BOOT_LINE is corrupted.
	SPR# 8746  This part of the target.nr file is no longer true 
	SPR# 8614  ppc860Siu.h macros are missing parameters.
	SPR# 20104 PPC BSPs make incorrect use of HI and HIADJ macros

	List of known-problems about this BSP:

	SPR# 20915 if_cpm driver is not entirely disabled when flags are set 
		   to IFF_DOWN
	SPR# 9254  on early revisions of the board, EDO_DRAM does not work 
		   with cache on 
	SPR# 24971 system clock interrupt is not instrumented
	SPR# 10000 worst case interrupt response time depends on the system
		   clock ISR execution time


RELEASE 1.1/3  Apr 98, re-release
	Added support for the MPC8xxFADS mother/daughter boards.  Uses SCC2
	for 823/850 daughterboards.

RELEASE 1.1/2  Jan 97, Tornado 1.0.1 re-release
	Added a macro DEFAULT_POWER_MGT_MODE to select the default
	power mode.  Turned off cache when EDO dram is selected.

RELEASE 1.1/1  FCS, Nov 1996,  (ADS860_1_1_1)
	
	This release is the first FCS release of the ads860 BSP against
	Tornado 1.0 PPC (FCS). The same BSP is used by the PowerPC 821
	and PowerPC 860.

	The default BSP configuration is for a MPC821/860ADS REV A
	board with either a MPC821 REV A.1 or MPC860 REV A.2 and DRAM
	NO EDO.

	For the MPC821/860ADS REV A board with EDO DRAM the macro EDO_DRAM
	located in config.h should be changed from #undef to #define. 
	The EDO DRAM hangs the CPU when the caches are turned on.
	Consequently the instruction  and data cache are turned off when
	the EDO DRAM is selected.  The EDO DRAM is not supported by 
	the MPC821/860ADS REV PILOT or ENG boards. 

	The MPC821/860ADS REV PILOT or ENG boards are detected dynamically
	and VxWorks performs the initialization according the board revision.

	With the MPC821/860 REV 0.2 or 0.3 CPUs, caches and MMUs should be
	disabled; otherwise, VxWorks hangs the board.

	The UPM (User Programmable Machine) is initialized according the
	SPLL frequency, the DRAM speed (60 or 70 ns), and whether EDO
	capability is supported or not. The UPM is initialized once by
	the romInit() function located in romInit.s.
	Two sets of UPM initialization tables are provided: one for a
	SPLL frequency of 25MHz and one for 50MHz. Select the 25MHz set
	only when the SPLL frequency is 25MHz. If the SPLL
	frequency is different from 25MHz (for example, 24 MHz), VxWorks 
	is not reliable when cache is enabled.  For all other frequencies,
	select the UPM table for 50MHz.  Performance is optimized only
	for 50MHz, but VxWorks is reliable.

RELEASE 1.1/0  Beta, Jun 1996,  (ADS860_1_1_0)

	This release is the first release of the ads860 BSP against
	Tornado 1.0 PPC (Beta). The same BSP is used by the PowerPC 821
	and PowerPC 860. 
	

        CAVEATS:

        1) Due to different silicon bugs the data and instruction cache is
	   turned off.