sample.c

2004年黄河R3000最终程序！个人编写

/******************************************************************************
      2004.07最终数采烧入程序 
	test out SPI driver with an  ADS8321/EB chip. Uses serial channel B for
	the SPI data.

	PB7 acts as the CS line on the ADS
	PB0 is the serial B clock line(SCLK)


	PC5 is the data input(MISO)

	Reads three bytes worth with each chip select.
	The first six bits are not part of the data. They are always  0 .
	 This is followed by 16 bits of data for the sample, and
	then 2 extra bits.

	add MUX select functions

	after 10ms interrupt

******************************************************************************/
#class auto
#define SPI_SER_B
#define SPI_CLK_DIVISOR 3 // or 2( fre.=2MHz)


#define CINBUFSIZE 	255
#define COUTBUFSIZE  255

#define MY_IP_ADDRESS 	"202.206.44.9"
#define MY_NETMASK 		"255.255.255.0"
#define  PORT 		6666


#memmap xmem
#use "dcrtcp.lib"
#use "spi.lib"

int Tout,wd;		//10ms is right
int ADComplete;	//16CH A/D is complete
int counter;
char adc_reading[3];
int adc_sample0;
int adc_sample1;
int adc_sample2;
int adc_sample3;
int adc_sample[17];

unsigned int i,flag;

void  timerb_isr();

void main()
{
   tcp_Socket socket;
   Tout=0;
	ADComplete=0;
	counter=18;
	adc_sample[0]=0x2000;
   flag=0;
   WrPortI(PFDDR, &PFDDRShadow,0xff);   //define the port F direction as output
   WrPortI(PEDDR, &PEDDRShadow,0xff);
	SPIinit();
	BitWrPortI(PEDR, &PEDRShadow, 0, 6);	  // chip select low
  	SPIRead(adc_reading,3);                  //to protect the first reading correct
  	BitWrPortI(PEDR, &PEDRShadow, 1, 6);	   // chip select high

#if __SEPARATE_INST_DATA__
	interrupt_vector timerb_intvec timerb_isr;
#else
	SetVectIntern(0x0B, timerb_isr);	   // set up ISR
#endif

	WrPortI(TBCR, &TBCRShadow, 0x09);	// clock timer B with (perclk/8) and
													//     set interrupt level to 1
	WrPortI(TBL1R, NULL, 0x00);			// set initial match!
	WrPortI(TBM1R, NULL, 0x00);
//   WrPortI(WDTCR, NULL, 0x53);
   wd=VdGetFreeWd(255);
   sock_init();
	WrPortI(PBDDR, &PBDDRShadow,0xff);	//direction outupt
	WrPortI (PBDR,NULL,0xff );			//	PB Output ff

   tcp_listen(&socket,PORT,0,0,NULL,0);

	while(!sock_established(&socket) && sock_bytesready(&socket)==-1)
		{
			tcp_tick(NULL);
      }
WrPortI(TBCSR, &TBCSRShadow, 0x03);	// enable timer B and B1 match interrupts

while(1)
{
   //printf("%d \n",Tout);
	if(pd_havelink(0)==0)
	{
      tcp_listen(&socket,PORT,0,0,NULL,0);
      while(!sock_established(&socket) && sock_bytesready(&socket)==-1)
		tcp_tick(NULL);
   }

	do
	{
		if(Tout==1)
  		{
  	  		Tout=0;
    		counter=18;
    		for(i=1;i<17;i++)   //  read 16 channel data
    		{
      		WrPortI(PADR, &PADRShadow, 0x00);
      		WrPortI(PFDR, &PFDRShadow,i);    //channel selection

     		 	BitWrPortI(PEDR, &PEDRShadow, 0, 6);	// chip select low
      		SPIRead(adc_reading,3);               //read 3 bytes
      		BitWrPortI(PEDR, &PEDRShadow, 1, 6);	// chip select high

				adc_sample0 = (adc_reading[0] <<6) + (adc_reading[1]>>2)&0xff;
				adc_sample1 = (adc_reading[1] <<6) + (adc_reading[2]>>2)&0xff;  //data processing
	  			adc_sample2=(adc_sample1<<8)+adc_sample0;
            flag=adc_sample2&0x8000;
		      if (flag==0x8000)
             {
                 adc_sample3=~adc_sample2+0x0001;
		           adc_sample3=adc_sample2;
                 adc_sample[i]=adc_sample3;
             }else adc_sample[i]=adc_sample2;
   	 	}
  			ADComplete=1;

		}

		if (ADComplete==1)
		{
			if(sock_fastwrite(&socket,adc_sample,34)==-1)
			{
				tcp_listen(&socket,PORT,0,0,NULL,0);

				while(!sock_established(&socket) && sock_bytesready(&socket)==-1)

            tcp_tick(NULL);

         }
			ADComplete=0;
         VdHitWd(wd);


		}
	}while(tcp_tick(&socket));

}
}


////////////////////////////////////////////////////////////////////////////////
// interrupt routine for timer B
//
//  This is called whenever _either_ B1 or B2 matches the timer.  If you are
//  using both of them, you need to check the TBCSR register to see which one
//  triggered the interrupt (you need to read that register anyway to clear
//  the flag).
//
////////////////////////////////////////////////////////////////////////////////

#asm
timerb_isr::
	push	af							; save registers
	push	hl

	ioi	ld a, (TBCSR)			; load B1, B2 interrupt flags (clears flag); this
										; should be done as soon as possible in the ISR
	ld		hl, (counter)
	dec	hl						; decrement counter
	ld		(counter),hl
   ld    a, (counter)
   and 	0xff
	jr		nz, zhishu          ;if A not zero load B1 counter
	ld	   hl, PADR
   ld 	a,0x01
	ld    (Tout),a

zhishu:
   ld		a, 00h
	ioi	ld (TBL1R), a
	ld		a, 00h			      ; set up next B1 match (at timer=0000h)
	ioi	ld (TBM1R), a

done:			                  ;	register after every interrupt!
	pop	hl							; restore registers
	pop	af

	ipres								; restore interrupts
	ret								; return
#endasm