44binit.s

BB40X的bootloader源代码

;****************************************************************************
;44binit.s
;Initialization for S3C44B0X
;
; This source file is taken from SAMSUNG demo code for S3C44B0X
;****************************************************************************
 
	GET inc\option.s
	GET inc\memcfg.s

;****************************************************************************
;Memory Space
;GCS6 64M 16bit(8MB) DRAM/SDRAM(0xc000000-0xc7fffff)
;APP        RAM=0xc000000~0xc7effff 
;44BMON     RAM=0xc7f0000-0xc7fffff
;STACK         =0xc7ffa00      

;****************************************************************************
;Interrupt control
INTPND      EQU 0x01e00004
INTMOD      EQU 0x01e00008
INTMSK      EQU 0x01e0000c
I_ISPR      EQU 0x01e00020
I_CMST      EQU 0x01e0001c


;****************************************************************************
;Part G
PCONG		EQU	0x01d20040
PDATG		EQU	0x01d20044
PUPG		EQU	0x01d20048
EXTINT		EQU	0x01d20050
	

;****************************************************************************
;Watch Dog
WTCON       EQU 0x01d30000

;****************************************************************************
;System clock
PLLCON      EQU 0x01d80000
CLKCON      EQU 0x01d80004
LOCKTIME    EQU 0x01d8000c
  
;****************************************************************************
;Fresh control
REFRESH     EQU 0x01c80024

;****************************************************************************
;BDMA destination
BDIDES0     EQU 0x1f80008
BDIDES1     EQU 0x1f80028

;****************************************************************************
;const definition
USERMODE    EQU 0x10
FIQMODE     EQU 0x11
IRQMODE     EQU 0x12
SVCMODE     EQU 0x13
ABORTMODE   EQU 0x17
UNDEFMODE   EQU 0x1b
MODEMASK    EQU 0x1f
NOINT       EQU 0xc0

;****************************************************************************
;Compiler check
    GBLL    THUMBCODE
    [ {CONFIG} = 16 
THUMBCODE SETL  {TRUE}
    CODE32
    |   
THUMBCODE SETL  {FALSE}
    ]

    [ THUMBCODE
    CODE32   ;for start-up code for Thumb mode
    ]

    MACRO
$HandlerLabel HANDLER $HandleLabel

;****************************************************************************
$HandlerLabel
    sub     sp,sp,#4            ;decrement sp(to store jump address)
    stmfd   sp!,{r0}            ;PUSH the work register to stack(lr does't push because it return to original address)
    ldr     r0,=$HandleLabel    ;load the address of HandleXXX to r0
    ldr     r0,[r0]             ;load the contents(service routine start address) of HandleXXX
    str     r0,[sp,#4]          ;store the contents(ISR) of HandleXXX to stack
    ldmfd   sp!,{r0,pc}         ;POP the work register and pc(jump to ISR)
    MEND

    IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT  |Image$$ZI$$Base|   ; Base and limit of area
    IMPORT  |Image$$ZI$$Limit|  ; to zero initialise

    IMPORT  Main                ; The main entry of mon program 

    AREA    Init,CODE,READONLY

;****************************************************************************
    ENTRY     ;Asm Entry
    b      ResetHandler  ;for debug    
    ldr    pc, =0x0C000004
    ldr    pc, =0x0C000008
    ldr    pc, =0x0C00000C
    ldr    pc, =0x0C000010
    ldr    pc, =0x0C000014
    ldr    pc, =0x0C000018
    ldr    pc, =0x0C00001C
    

;****************************************************************************
; Reset handler, start point

ResetHandler
    ldr     r0,=WTCON       ;Disable watchdog
    ldr     r1,=0x0     
    str     r1,[r0]

    ldr     r0,=INTMSK
    ldr     r1,=0x07ffffff  ;Disable all interrupt
    str     r1,[r0]
    
    ldr		r0,=INTMOD
    ldr		r1,=0x0
    str		r1,[r0]
    
    ldr		r0,=PCONG
    ldr		r1,=0xC0
    str		r1,[r0]
    
    ldr		r0,=PDATG
    ldr		r1,=0xff
    str		r1,[r0]
    
    ldr		r0,=PUPG
    ldr		r1,=0x0
    str		r1,[r0]
    
    ldr		r0,=EXTINT
    ldr		r1,=0x4000
    str		r1,[r0] 

    ;Setup clock register
    ldr r0,=LOCKTIME
    ldr r1,=0xfff
    str r1,[r0]

    [ PLLONSTART
     ldr r0,=PLLCON      
     ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)    ;Set system clock
     str r1,[r0]
    ]

    ldr     r0,=CLKCON     
    ldr     r1,=0x7ff8       ;Enable clock functions
    str     r1,[r0]


;****************************************************************************
;Set memory controller
    ldr     r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr     r0,=0x01c80000  ;BWSCON Address
    stmia   r0,{r1-r13}

;****************************************************************************
;Set stack
    ldr     sp, =SVCStack
    bl      InitStacks


;****************************************************************************
;Copy and paste RW data/zero initialized data

    LDR     r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
    LDR     r1, =|Image$$RW$$Base|  ; and RAM copy
    LDR     r3, =|Image$$ZI$$Base|  
  ;Zero init base => top of initialised data
      
    CMP     r0, r1      ; Check that they are different
    BEQ     %F1
0   
    CMP     r1, r3      ; Copy init data
    LDRCC   r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4     
    STRCC   r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
    BCC     %B0
1   
    LDR     r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    MOV     r2, #0
2   
    CMP     r3, r1      ; Zero init
    STRCC   r2, [r3], #4
    BCC     %B2

;===========================Here go to C code=============================
    [ :LNOT:THUMBCODE
     BL  Main      ;Go into code
     B .           
    ]
;=========================================================================

    [ THUMBCODE       ;for start-up code for Thumb mode
     orr     lr,pc,#1
     bx      lr
     CODE16
     bl      Main      ;Go to C code
     b       .
     CODE32
    ]

;****************************************************
;Initlize stack
;****************************************************
InitStacks
  ;Don't use DRAM,such as stmfd,ldmfd......
  ;SVCstack is initialized before
  ;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

    mrs     r0,cpsr
    bic     r0,r0,#MODEMASK
    orr     r1,r0,#UNDEFMODE|NOINT
    msr     cpsr_cxsf,r1    ;UndefMode
    ldr     sp,=UndefStack
  
    orr     r1,r0,#ABORTMODE|NOINT
    msr     cpsr_cxsf,r1        ;AbortMode
    ldr     sp,=AbortStack

    orr     r1,r0,#IRQMODE|NOINT
    msr     cpsr_cxsf,r1        ;IRQMode
    ldr     sp,=IRQStack
  
    orr     r1,r0,#FIQMODE|NOINT
    msr     cpsr_cxsf,r1        ;FIQMode
    ldr     sp,=FIQStack

    bic     r0,r0,#MODEMASK|NOINT
    orr     r1,r0,#SVCMODE
    msr     cpsr_cxsf,r1        ;SVCMode
    ldr     sp,=SVCStack

  ;USER mode is not initialized.
    mov     pc,lr ;The LR register may be not valid for the mode changes.


SMRDATA DATA
;*****************************************************************
;Config Dram controller
;*****************************************************************

;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz. 

;bank0  16bit BOOT ROM
;bank1  8bit NandFlash
;bank2  16bit IDE
;bank3  8bit UDB
;bank4  rtl8019
;bank5  ext
;bank6  16bit SDRAM
;bank7  16bit SDRAM
  [ BUSWIDTH=16
    DCD 0x11111112        ;Bank0=16bit BootRom(AT29C010A*2) :0x0
      ; BUSWIDTH=16
      ; DCD 0x11111111  ;Bank0=OM[1:0], Bank1~Bank7=32bit
  ]
  DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
  DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1 
  DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
  DCD 0x7ffc ;GCS3
  DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
  DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
  [ BDRAMTYPE="DRAM" 
      DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN))  ;GCS6 check the MT value in parameter.a
      DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN))  ;GCS7
  | ;"SDRAM"
    DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  ;GCS6
    DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  ;GCS7
  ]
  DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
  DCD 0x10      ;SCLK power down mode, BANKSIZE 32M/32M
  DCD 0x20      ;MRSR6 CL=2clk
  DCD 0x20      ;MRSR7



  ALIGN

  AREA RamData, DATA, READWRITE

  ^ (_ISR_STARTADDRESS-0x500)
        
UserStack   # 256 ;c1(c7)ffa00
SVCStack    # 256 ;c1(c7)ffb00
UndefStack  # 256 ;c1(c7)ffc00
AbortStack  # 256 ;c1(c7)ffd00
IRQStack    # 256 ;c1(c7)ffe00
FIQStack    # 0   ;c1(c7)fff00
 END
;****************************************************************************