bt.s

ＡＶＲ ＩＣＣ基于ＡＶＲ单片机的ＬＥＤ显示程序！

	.module bt.c
	.area data(ram, con, rel)
_shu::
	.blkb 2
	.area idata
	.byte 192,249
	.area data(ram, con, rel)
	.blkb 2
	.area idata
	.byte 164,176
	.area data(ram, con, rel)
	.blkb 2
	.area idata
	.byte 153,146
	.area data(ram, con, rel)
	.blkb 2
	.area idata
	.byte 130,248
	.area data(ram, con, rel)
	.blkb 2
	.area idata
	.byte 128,144
	.area data(ram, con, rel)
	.blkb 2
	.area idata
	.byte 191,255
	.area data(ram, con, rel)
	.dbfile D:\ele\AVR\ICC\cp\biaotao/bt.h
	.dbsym e shu _shu A[12:12]c
_tm::
	.blkb 2
	.area idata
	.byte 11,11
	.area data(ram, con, rel)
	.dbfile D:\ele\AVR\ICC\cp\biaotao/bt.h
	.blkb 2
	.area idata
	.byte 11,11
	.area data(ram, con, rel)
	.dbfile D:\ele\AVR\ICC\cp\biaotao/bt.h
	.dbsym e tm _tm A[4:4]c
	.area text(rom, con, rel)
	.dbfile D:\ele\AVR\ICC\cp\biaotao/bt.h
	.dbfunc e port_init _port_init fV
	.even
_port_init::
	.dbline -1
	.dbline 55
; #include <iom8v.h>
; #include "bt.h"
; #include <macros.h>
; #include <eeprom.h>
; 
; #define uchar unsigned char
; #define unit unsigned int
; #define ulong unsigned long
; 
; 
; 
; #define xtal 8 
; #define fosc 8000000 //晶振8MHZ
; #define baud 9600	 //波特率
; 
; 
; #define out0 PORTD&=~0X02
; #define out1 PORTD|=0X02
; 
; #define be0 PORTB&=~0X40
; #define be1 PORTB|=0X80
; 
; #define Set     ((PIND&0X04)==0x04)                          //key
; #define Add     ((PIND&0X02)==0x02)
; #define Sub     ((PIND&0X01)==0x01)  
; #define Store   (1) 
; 
; uchar n,ORDER,j;
; 
; 
; uchar t,i,j,m,s,m1,s1;
; uchar mm[2]={0xbf,0xbf};
; uchar date[9]={1};
; unit dat;
; uchar lock,dp,ready,start,win=1,xian=0;
; 
; 
; unsigned long adc_rel[8];//AD转换结果
; unsigned char adc_mux;//AD通道
; 
; //ADC initialize
; // Cpbversipb time: 3uS
; void adc_init(void)
; {
;  ADCSRA = 0x00; //disable adc
;  ADMUX = 0x40; //select adc input 0  00-ref  01-avcc 11-2.56
;  ACSR  = 0x80;
;  ADCSRA=(1<<ADEN)|(1<<ADSC)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0) ;//64分频
; }
; 
; 
; 
; unit cw(uchar mux)          ///*****检测信号*****///
; {
;  ADMUX=(1<<REFS0)|(mux&0x0f);
	.dbline 56
;  ADCSRA|=0x40;
	ldi R24,48
	out 0x18,R24
	.dbline 57
;  del(500);
	ldi R24,60
	out 0x17,R24
	.dbline 58
;  return(ADC);
	ldi R24,6
	out 0x15,R24
	.dbline 59
; }
	ldi R24,15
	out 0x14,R24
	.dbline 60
; 
	ldi R24,223
	out 0x12,R24
	.dbline 61
; unit cw1(uchar mux)          ///*****检测信号*****///
	ldi R24,216
	out 0x11,R24
	.dbline -2
L1:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e DAT _DAT fV
;              x -> R16
	.even
_DAT::
	.dbline -1
	.dbline 65
; {
; ulong adc_rel,a;
; uchar i;
;  for(i=0;i<100;i++)
	.dbline 66
	mov R24,R16
	andi R24,1
	cpi R24,1
	brne L3
	.dbline 66
	sbi 0x12,6
	rjmp L4
L3:
	.dbline 66
;   {
	cbi 0x12,6
L4:
	.dbline 67
	mov R24,R16
	andi R24,2
	cpi R24,2
	brne L5
	.dbline 67
	sbi 0x12,7
	rjmp L6
L5:
	.dbline 67
;   adc_rel+=cw(mux);
	cbi 0x12,7
L6:
	.dbline 68
	mov R24,R16
	andi R24,4
	cpi R24,4
	brne L7
	.dbline 68
	sbi 0x18,5
	rjmp L8
L7:
	.dbline 68
;   WDR();
	cbi 0x18,5
L8:
	.dbline 69
	mov R24,R16
	andi R24,8
	cpi R24,8
	brne L9
	.dbline 69
	sbi 0x15,1
	rjmp L10
L9:
	.dbline 69
;   } 
	cbi 0x15,1
L10:
	.dbline 70
	mov R24,R16
	andi R24,16
	cpi R24,16
	brne L11
	.dbline 70
	sbi 0x15,2
	rjmp L12
L11:
	.dbline 70
;   a=adc_rel;
	cbi 0x15,2
L12:
	.dbline 71
	mov R24,R16
	andi R24,32
	cpi R24,32
	brne L13
	.dbline 71
	sbi 0x12,4
	rjmp L14
L13:
	.dbline 71
;   adc_rel=0;
	cbi 0x12,4
L14:
	.dbline 72
	mov R24,R16
	andi R24,64
	cpi R24,64
	brne L15
	.dbline 72
	sbi 0x12,3
	rjmp L16
L15:
	.dbline 72
;  return (unit)(a/100); 
	cbi 0x12,3
L16:
	.dbline 73
	mov R24,R16
	andi R24,128
	cpi R24,128
	brne L17
	.dbline 73
	sbi 0x18,4
	rjmp L18
L17:
	.dbline 73
	cbi 0x18,4
L18:
	.dbline -2
L2:
	.dbline 0 ; func end
	ret
	.dbsym r x 16 c
	.dbend
	.dbfunc e del _del fV
;           time -> R16,R17
	.even
_del::
	.dbline -1
	.dbline 79
; }
; 
; 
; //TIMER1 initialize - prescale:1024
; // WGM: 0) Normal, TOP=0xFFFF
; // desired value: 2Hz
; // actual value:  2.000Hz (0.0%)
L20:
	.dbline 81
; void timer1_init(void)
; {
	.dbline 82
;  TCCR1B = 0x00; //stop
	subi R16,1
	sbci R17,0
	.dbline 83
;  TCNT1H = 0xF0; //setup
L21:
	.dbline 84
;  TCNT1L = 0xBE;
	ldi R24,1
	ldi R25,0
	cp R24,R16
	cpc R25,R17
	brlt L20
	.dbline -2
L19:
	.dbline 0 ; func end
	ret
	.dbsym r time 16 I
	.dbend
	.dbfunc e A _A fV
	.even
_A::
	.dbline -1
	.dbline 89
;  OCR1AH = 0x07;
;  OCR1AL = 0xA1;
;  OCR1BH = 0x07;
;  OCR1BL = 0xA1;
;  ICR1H  = 0x07;
	.dbline 90
;  ICR1L  = 0xA1;
	sbi 0x18,2
	.dbline 90
	ldi R24,<_shu
	ldi R25,>_shu
	lds R30,_tm
	clr R31
	add R30,R24
	adc R31,R25
	ldd R16,z+0
	rcall _DAT
	.dbline 90
	ldi R16,225
	ldi R17,0
	rcall _del
	.dbline 90
	cbi 0x18,2
	.dbline 90
	ldi R16,255
	rcall _DAT
	.dbline 90
	ldi R16,5
	ldi R17,0
	rcall _del
	.dbline 90
	wdr
	.dbline 91
;  TCCR1A = 0x00;
	sbi 0x18,3
	.dbline 91
	ldi R24,<_shu
	ldi R25,>_shu
	lds R30,_tm+1
	clr R31
	add R30,R24
	adc R31,R25
	ldd R16,z+0
	rcall _DAT
	.dbline 91
	ldi R16,226
	ldi R17,0
	rcall _del
	.dbline 91
	cbi 0x18,3
	.dbline 91
	ldi R16,255
	rcall _DAT
	.dbline 91
	ldi R16,5
	ldi R17,0
	rcall _del
	.dbline 91
	wdr
	.dbline 92
;  TCCR1B = 0x05; //start Timer
	sbi 0x15,0
	.dbline 92
	ldi R24,<_shu
	ldi R25,>_shu
	lds R30,_tm+2
	clr R31
	add R30,R24
	adc R31,R25
	ldd R16,z+0
	rcall _DAT
	.dbline 92
	ldi R16,225
	ldi R17,0
	rcall _del
	.dbline 92
	cbi 0x15,0
	.dbline 92
	ldi R16,255
	rcall _DAT
	.dbline 92
	ldi R16,5
	ldi R17,0
	rcall _del
	.dbline 92
	wdr
	.dbline 93
; }
	sbi 0x15,3
	.dbline 93
	ldi R24,<_shu
	ldi R25,>_shu
	lds R30,_tm+3
	clr R31
	add R30,R24
	adc R31,R25
	ldd R16,z+0
	rcall _DAT
	.dbline 93
	ldi R16,226
	ldi R17,0
	rcall _del
	.dbline 93
	cbi 0x15,3
	.dbline 93
	ldi R16,255
	rcall _DAT
	.dbline 93
	ldi R16,5
	ldi R17,0
	rcall _del
	.dbline 93
	wdr
	.dbline -2
L23:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e bee _bee fV
;              j -> R20,R21
;             j1 -> R12,R13
;         spfreq -> R22,R23
;              k -> R14,R15
;           tone -> R20,R21
;      soundlong -> R10,R11
	.even
_bee::
	rcall push_gset5
	movw R20,R18
	movw R10,R16
	.dbline -1
	.dbline 98
; 
; 
; //Watchdog initialize
; // prescale: 512K
; void watchdog_init(void)
	.dbline 100
; {
;  WDR(); //this prevents a timout on enabling
	ldi R16,15000
	ldi R17,58
	movw R18,R20
	rcall div16u
	movw R22,R16
	lsr R23
	ror R22
	.dbline 101
;  WDTCR = 0x0E; //WATCHDOG ENABLED - dont forget to issue WDRs
	clr R20
	clr R21
	rjmp L31
L28:
	.dbline 102
; }
	clr R12
	clr R13
	rjmp L35
L32:
	.dbline 103
; 
	.dbline 104
; //call this routine to initialize all peripherals
	cbi 0x18,6
	.dbline 105
	clr R14
	clr R15
	rjmp L39
L36:
	.dbline 105
L37:
	.dbline 105
	movw R24,R14
	adiw R24,1
	movw R14,R24
L39:
	.dbline 105
; void init_devices(void)
	cp R14,R22
	cpc R15,R23
	brlo L36
	.dbline 106
; {
	sbi 0x18,7
	.dbline 107
	clr R14
	clr R15
	rjmp L43
L40:
	.dbline 107
L41:
	.dbline 107
	movw R24,R14
	adiw R24,1
	movw R14,R24
L43:
	.dbline 107
	cp R14,R22
	cpc R15,R23
	brlo L40
	.dbline 108
	wdr
	.dbline 109
L33:
	.dbline 102
	movw R24,R12
	adiw R24,1
	movw R12,R24
L35:
	.dbline 102
	movw R24,R12
	cpi R24,20
	ldi R30,0
	cpc R25,R30
	brlo L32
L29:
	.dbline 101
	subi R20,255  ; offset = 1
	sbci R21,255
L31:
	.dbline 101
	cp R20,R10
	cpc R21,R11
	brlo L28
	.dbline 110
;  //stop errant interrupts until set up
;  CLI(); //disable all interrupts
;  port_init();
;  watchdog_init();
	sbi 0x18,7
	.dbline -2
L27:
	rcall pop_gset5
	.dbline 0 ; func end
	ret
	.dbsym r j 20 i
	.dbsym r j1 12 i
	.dbsym r spfreq 22 i
	.dbsym r k 14 i
	.dbsym r tone 20 i
	.dbsym r soundlong 10 i
	.dbend
	.dbfunc e delay _delay fV
;             i2 -> R20,R21
;              n -> R22,R23
	.even
_delay::
	rcall push_gset2
	movw R22,R16
	.dbline -1
	.dbline 116
;  timer1_init();
;  adc_init();
;  
;  MCUCR = 0x00;
;  GICR  = 0x00;
;  TIMSK = 0x04; //timer interrupt sources
	.dbline 117
;  SEI(); //re-enable interrupts
	clr R20
	clr R21
	rjmp L46
L45:
	.dbline 119
	.dbline 120
	rcall _A
	.dbline 120
	subi R20,255  ; offset = 1
	sbci R21,255
	.dbline 120
	wdr
	.dbline 121
L46:
	.dbline 118
;  //all peripherals are now initialized
	cp R20,R22
	cpc R21,R23
	brlo L45
	.dbline -2
L44:
	rcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r i2 20 i
	.dbsym r n 22 i
	.dbend
	.dbfunc e show _show fV
;              i -> R20
;            dat -> R22,R23
;              n -> R10
	.even
_show::
	rcall push_gset3
	movw R22,R18
	mov R10,R16
	.dbline -1
	.dbline 126
; }
; 
; 
; 
; 
; 
; #pragma interrupt_handler timer1_ovf_isr:14
; void timer1_ovf_isr(void)
	.dbline 128
	clr R20
	rjmp L52
L49:
	.dbline 128
	.dbline 129
	ldi R18,10
	ldi R19,0
	movw R16,R22
	rcall mod16u
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	std z+0,R16
	.dbline 130
	ldi R18,10
	ldi R19,0
	movw R16,R22
	rcall div16u
	movw R22,R16
	.dbline 131
L50:
	.dbline 128
	inc R20
L52:
	.dbline 128
; {
; 
	cpi R20,4
	brlo L49
	.dbline 132
;  t++;
;  dp=~dp;
;  if(t==2) 
;   {
	ldi R20,3
	rjmp L54
L53:
	.dbline 133
	.dbline 134
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,11
	std z+0,R24
	.dbline 135
	dec R20
	.dbline 136
L54:
	.dbline 133
;   t=0;s++;s1++; 
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	tst R2
	brne L56
	clr R2
	cp R2,R20
	brlo L53
L56:
	.dbline 137
;   if(s==60)
;    { 
;    date[2]++;m1++;s=0;
;    EEPROMwrite(23,date[2]); 
	sts _tm+3,R10
	.dbline 138
;    if(date[2]>59) 
	rcall _A
	.dbline -2
L48:
	rcall pop_gset3
	.dbline 0 ; func end
	ret
	.dbsym r i 20 c
	.dbsym r dat 22 i
	.dbsym r n 10 c
	.dbend
	.dbfunc e show4 _show4 fV
;              i -> R20
;            dat -> R22,R23
	.even
_show4::
	rcall push_gset2
	movw R22,R16
	.dbline -1
	.dbline 144
;     {
; 	date[2]=0; date[1]++; bee(500,400);
; 	if(date[1]>23) date[1]=0; 
; 	EEPROMwrite(23,date[2]); EEPROMwrite(21,date[1]); 
; 	}
;    if((date[1]==date[3])&&(date[2]==date[4])&&(date[0]%2==1))
	.dbline 146
	clr R20
	rjmp L62
L59:
	.dbline 146
	.dbline 147
	ldi R18,10
	ldi R19,0
	movw R16,R22
	rcall mod16u
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	std z+0,R16
	.dbline 148
	ldi R18,10
	ldi R19,0
	movw R16,R22
	rcall div16u
	movw R22,R16
	.dbline 149
L60:
	.dbline 146
	inc R20
L62:
	.dbline 146
;     {start=1; bee(1000,400); }
;    }
	cpi R20,4
	brlo L59
	.dbline 150
;   } 
;  TCNT1H = 0xF0; //setup
;  TCNT1L = 0xBE;
; }
	ldi R20,3
	rjmp L64
L63:
	.dbline 152
	.dbline 153
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,11
	std z+0,R24
	.dbline 154
	dec R20
	.dbline 155
L64:
	.dbline 151
; 
	ldi R24,<_tm
	ldi R25,>_tm
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	tst R2
	brne L66
	clr R2
	cp R2,R20
	brlo L63
L66:
	.dbline 156
; 
; 
; 
; 
; 
	rcall _A
	.dbline -2
L58:
	rcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r i 20 c