biaotoum8.lst

ＡＶＲ ＩＣＣ基于ＡＶＲ单片机的ＬＥＤ显示程序！

    0169 018B      MOVW	R16,R22
    016A D3B7      RCALL	div16u
    016B 01B8      MOVW	R22,R16
    016C 9543      INC	R20
    016D 3044      CPI	R20,4
    016E F368      BCS	0x015C
(0149)         } 
(0150)     i=3;
    016F E043      LDI	R20,3
    0170 C009      RJMP	0x017A
(0151)     while(tm[i]==0&&i>0)
(0152) 	   {
(0153)        tm[i]=11;
    0171 E68C      LDI	R24,0x6C
    0172 E090      LDI	R25,0
    0173 2FE4      MOV	R30,R20
    0174 27FF      CLR	R31
    0175 0FE8      ADD	R30,R24
    0176 1FF9      ADC	R31,R25
    0177 E08B      LDI	R24,0xB
    0178 8380      STD	Z+0,R24
(0154)        i--;
    0179 954A      DEC	R20
    017A E68C      LDI	R24,0x6C
    017B E090      LDI	R25,0
    017C 2FE4      MOV	R30,R20
    017D 27FF      CLR	R31
    017E 0FE8      ADD	R30,R24
    017F 1FF9      ADC	R31,R25
    0180 8020      LDD	R2,Z+0
    0181 2022      TST	R2
    0182 F419      BNE	0x0186
    0183 2422      CLR	R2
    0184 1624      CP	R2,R20
    0185 F358      BCS	0x0171
(0155)         } 
(0156) A();
    0186 DF09      RCALL	_A
    0187 D43D      RCALL	pop_gset2
    0188 9508      RET
FILE: D:\ele\AVR\ICC\cp\biaotao\bt.c
(0001) #include <iom8v.h>
(0002) #include "bt.h"
(0003) #include <macros.h>
(0004) #include <eeprom.h>
(0005) 
(0006) #define uchar unsigned char
(0007) #define unit unsigned int
(0008) #define ulong unsigned long
(0009) 
(0010) 
(0011) 
(0012) #define xtal 8 
(0013) #define fosc 8000000 //晶振8MHZ
(0014) #define baud 9600	 //波特率
(0015) 
(0016) 
(0017) #define out0 PORTD&=~0X02
(0018) #define out1 PORTD|=0X02
(0019) 
(0020) #define be0 PORTB&=~0X40
(0021) #define be1 PORTB|=0X80
(0022) 
(0023) #define Set     ((PIND&0X04)==0x04)                          //key
(0024) #define Add     ((PIND&0X02)==0x02)
(0025) #define Sub     ((PIND&0X01)==0x01)  
(0026) #define Store   (1) 
(0027) 
(0028) uchar n,ORDER,j;
(0029) 
(0030) 
(0031) uchar t,i,j,m,s,m1,s1;
(0032) uchar mm[2]={0xbf,0xbf};
(0033) uchar date[9]={1};
(0034) unit dat;
(0035) uchar lock,dp,ready,start,win=1,xian=0;
(0036) 
(0037) 
(0038) unsigned long adc_rel[8];//AD转换结果
(0039) unsigned char adc_mux;//AD通道
(0040) 
(0041) //ADC initialize
(0042) // Cpbversipb time: 3uS
(0043) void adc_init(void)
(0044) {
(0045)  ADCSRA = 0x00; //disable adc
_adc_init:
    0189 2422      CLR	R2
    018A B826      OUT	0x06,R2
(0046)  ADMUX = 0x40; //select adc input 0  00-ref  01-avcc 11-2.56
    018B E480      LDI	R24,0x40
    018C B987      OUT	0x07,R24
(0047)  ACSR  = 0x80;
    018D E880      LDI	R24,0x80
    018E B988      OUT	0x08,R24
(0048)  ADCSRA=(1<<ADEN)|(1<<ADSC)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0) ;//64分频
    018F EC87      LDI	R24,0xC7
    0190 B986      OUT	0x06,R24
    0191 9508      RET
_cw:
  mux                  --> R20
    0192 D442      RCALL	push_gset1
    0193 2F40      MOV	R20,R16
(0049) }
(0050) 
(0051) 
(0052) 
(0053) unit cw(uchar mux)          ///*****检测信号*****///
(0054) {
(0055)  ADMUX=(1<<REFS0)|(mux&0x0f);
    0194 2F84      MOV	R24,R20
    0195 708F      ANDI	R24,0xF
    0196 6480      ORI	R24,0x40
    0197 B987      OUT	0x07,R24
(0056)  ADCSRA|=0x40;
    0198 9A36      SBI	0x06,6
(0057)  del(500);
    0199 EF04      LDI	R16,0xF4
    019A E011      LDI	R17,1
    019B DEEC      RCALL	_del
(0058)  return(ADC);
    019C B104      IN	R16,0x04
    019D B115      IN	R17,0x05
    019E D439      RCALL	pop_gset1
    019F 9508      RET
_cw1:
  a                    --> Y+4
  adc_rel              --> Y+0
  i                    --> R10
  mux                  --> R12
    01A0 D42E      RCALL	push_gset4
    01A1 2EC0      MOV	R12,R16
    01A2 9728      SBIW	R28,0x8
(0059) }
(0060) 
(0061) unit cw1(uchar mux)          ///*****检测信号*****///
(0062) {
(0063) ulong adc_rel,a;
(0064) uchar i;
(0065)  for(i=0;i<100;i++)
    01A3 24AA      CLR	R10
    01A4 C015      RJMP	0x01BA
(0066)   {
(0067)   adc_rel+=cw(mux);
    01A5 2D0C      MOV	R16,R12
    01A6 DFEB      RCALL	_cw
    01A7 0118      MOVW	R2,R16
    01A8 2444      CLR	R4
    01A9 2455      CLR	R5
    01AA 01FE      MOVW	R30,R28
    01AB 8060      LDD	R6,Z+0
    01AC 8071      LDD	R7,Z+1
    01AD 8082      LDD	R8,Z+2
    01AE 8093      LDD	R9,Z+3
    01AF 0C62      ADD	R6,R2
    01B0 1C73      ADC	R7,R3
    01B1 1C84      ADC	R8,R4
    01B2 1C95      ADC	R9,R5
    01B3 01FE      MOVW	R30,R28
    01B4 8260      STD	Z+0,R6
    01B5 8271      STD	Z+1,R7
    01B6 8282      STD	Z+2,R8
    01B7 8293      STD	Z+3,R9
(0068)   WDR();
    01B8 95A8      WDR
    01B9 94A3      INC	R10
    01BA 2D8A      MOV	R24,R10
    01BB 3684      CPI	R24,0x64
    01BC F340      BCS	0x01A5
(0069)   } 
(0070)   a=adc_rel;
    01BD 01FE      MOVW	R30,R28
    01BE 8020      LDD	R2,Z+0
    01BF 8031      LDD	R3,Z+1
    01C0 8042      LDD	R4,Z+2
    01C1 8053      LDD	R5,Z+3
    01C2 01FE      MOVW	R30,R28
    01C3 8224      STD	Z+4,R2
    01C4 8235      STD	Z+5,R3
    01C5 8246      STD	Z+6,R4
    01C6 8257      STD	Z+7,R5
(0071)   adc_rel=0;
    01C7 E040      LDI	R20,0
    01C8 E050      LDI	R21,0
    01C9 E060      LDI	R22,0
    01CA E070      LDI	R23,0
    01CB 01FE      MOVW	R30,R28
    01CC 8340      STD	Z+0,R20
    01CD 8351      STD	Z+1,R21
    01CE 8362      STD	Z+2,R22
    01CF 8373      STD	Z+3,R23
(0072)  return (unit)(a/100); 
    01D0 E644      LDI	R20,0x64
    01D1 E050      LDI	R21,0
    01D2 E060      LDI	R22,0
    01D3 E070      LDI	R23,0
    01D4 01FE      MOVW	R30,R28
    01D5 8024      LDD	R2,Z+4
    01D6 8035      LDD	R3,Z+5
    01D7 8046      LDD	R4,Z+6
    01D8 8057      LDD	R5,Z+7
    01D9 937A      ST	R23,-Y
    01DA 936A      ST	R22,-Y
    01DB 935A      ST	R21,-Y
    01DC 934A      ST	R20,-Y
    01DD 0181      MOVW	R16,R2
    01DE 0192      MOVW	R18,R4
    01DF D35C      RCALL	div32u
    01E0 9628      ADIW	R28,0x8
    01E1 D3E7      RCALL	pop_gset4
    01E2 9508      RET
(0073) }
(0074) 
(0075) 
(0076) //TIMER1 initialize - prescale:1024
(0077) // WGM: 0) Normal, TOP=0xFFFF
(0078) // desired value: 2Hz
(0079) // actual value:  2.000Hz (0.0%)
(0080) void timer1_init(void)
(0081) {
(0082)  TCCR1B = 0x00; //stop
_timer1_init:
    01E3 2422      CLR	R2
    01E4 BC2E      OUT	0x2E,R2
(0083)  TCNT1H = 0xF0; //setup
    01E5 EF80      LDI	R24,0xF0
    01E6 BD8D      OUT	0x2D,R24
(0084)  TCNT1L = 0xBE;
    01E7 EB8E      LDI	R24,0xBE
    01E8 BD8C      OUT	0x2C,R24
(0085)  OCR1AH = 0x07;
    01E9 E087      LDI	R24,7
    01EA BD8B      OUT	0x2B,R24
(0086)  OCR1AL = 0xA1;
    01EB EA81      LDI	R24,0xA1
    01EC BD8A      OUT	0x2A,R24
(0087)  OCR1BH = 0x07;
    01ED E087      LDI	R24,7
    01EE BD89      OUT	0x29,R24
(0088)  OCR1BL = 0xA1;
    01EF EA81      LDI	R24,0xA1
    01F0 BD88      OUT	0x28,R24
(0089)  ICR1H  = 0x07;
    01F1 E087      LDI	R24,7
    01F2 BD87      OUT	0x27,R24
(0090)  ICR1L  = 0xA1;
    01F3 EA81      LDI	R24,0xA1
    01F4 BD86      OUT	0x26,R24
(0091)  TCCR1A = 0x00;
    01F5 BC2F      OUT	0x2F,R2
(0092)  TCCR1B = 0x05; //start Timer
    01F6 E085      LDI	R24,5
    01F7 BD8E      OUT	0x2E,R24
    01F8 9508      RET
(0093) }
(0094) 
(0095) 
(0096) //Watchdog initialize
(0097) // prescale: 512K
(0098) void watchdog_init(void)
(0099) {
(0100)  WDR(); //this prevents a timout on enabling
_watchdog_init:
    01F9 95A8      WDR
(0101)  WDTCR = 0x0E; //WATCHDOG ENABLED - dont forget to issue WDRs
    01FA E08E      LDI	R24,0xE
    01FB BD81      OUT	0x21,R24
    01FC 9508      RET
(0102) }
(0103) 
(0104) //call this routine to initialize all peripherals
(0105) void init_devices(void)
(0106) {
(0107)  //stop errant interrupts until set up
(0108)  CLI(); //disable all interrupts
_init_devices:
    01FD 94F8      BCLR	7
(0109)  port_init();
    01FE DE43      RCALL	_port_init
(0110)  watchdog_init();
    01FF DFF9      RCALL	_watchdog_init
(0111)  timer1_init();
    0200 DFE2      RCALL	_timer1_init
(0112)  adc_init();
    0201 DF87      RCALL	_adc_init
(0113)  
(0114)  MCUCR = 0x00;
    0202 2422      CLR	R2
    0203 BE25      OUT	0x35,R2
(0115)  GICR  = 0x00;
    0204 BE2B      OUT	0x3B,R2
(0116)  TIMSK = 0x04; //timer interrupt sources
    0205 E084      LDI	R24,4
    0206 BF89      OUT	0x39,R24
(0117)  SEI(); //re-enable interrupts
    0207 9478      BSET	7
    0208 9508      RET
_timer1_ovf_isr:
    0209 D3E2      RCALL	push_lset
(0118)  //all peripherals are now initialized
(0119) }
(0120) 
(0121) 
(0122) 
(0123) 
(0124) 
(0125) #pragma interrupt_handler timer1_ovf_isr:14
(0126) void timer1_ovf_isr(void)
(0127) {
(0128) 
(0129)  t++;
    020A 918000A9  LDS	R24,t
    020C 5F8F      SUBI	R24,0xFF
    020D 938000A9  STS	t,R24
(0130)  dp=~dp;
    020F 902000A0  LDS	R2,dp
    0211 9420      COM	R2
    0212 922000A0  STS	dp,R2
(0131)  if(t==2) 
    0214 3082      CPI	R24,2
    0215 F009      BEQ	0x0217
    0216 C061      RJMP	0x0278
(0132)   {
(0133)   t=0;s++;s1++; 
    0217 2422      CLR	R2
    0218 922000A9  STS	t,R2
    021A 918000A6  LDS	R24,s
    021C 5F8F      SUBI	R24,0xFF
    021D 938000A6  STS	s,R24
    021F 918000A4  LDS	R24,s1
    0221 5F8F      SUBI	R24,0xFF
    0222 938000A4  STS	s1,R24
(0134)   if(s==60)
    0224 918000A6  LDS	R24,s
    0226 338C      CPI	R24,0x3C
    0227 F009      BEQ	0x0229
    0228 C04F      RJMP	0x0278
(0135)    { 
(0136)    date[2]++;m1++;s=0;
    0229 91800074  LDS	R24,date+2
    022B 5F8F      SUBI	R24,0xFF
    022C 93800074  STS	date+2,R24
    022E 918000A5  LDS	R24,m1
    0230 5F8F      SUBI	R24,0xFF
    0231 938000A5  STS	m1,R24
    0233 922000A6  STS	s,R2
(0137)    EEPROMwrite(23,date[2]); 
    0235 91200074  LDS	R18,date+2
    0237 E107      LDI	R16,0x17
    0238 E010      LDI	R17,0
    0239 D3E5      RCALL	_EEPROMwrite
(0138)    if(date[2]>59) 
    023A E38B      LDI	R24,0x3B
    023B 90200074  LDS	R2,date+2
    023D 1582      CP	R24,R2
    023E F4F8      BCC	0x025E
(0139)     {
(0140) 	date[2]=0; date[1]++; bee(500,400);
    023F 2422      CLR	R2
    0240 92200074  STS	date+2,R2
    0242 91800073  LDS	R24,date+1
    0244 5F8F      SUBI	R24,0xFF
    0245 93800073  STS	date+1,R24
    0247 E920      LDI	R18,0x90
    0248 E031      LDI	R19,1
    0249 EF04      LDI	R16,0xF4
    024A E011      LDI	R17,1
    024B DE95      RCALL	_bee
(0141) 	if(date[1]>23) date[1]=0; 
    024C E187      LDI	R24,0x17
    024D 90200073  LDS	R2,date+1
    024F 1582      CP	R24,R2
    0250 F418      BCC	0x0254
    0251 2422      CLR	R2
    0252 92200073  STS	date+1,R2
(0142) 	EEPROMwrite(23,date[2]); EEPROMwrite(21,date[1]); 
    0254 91200074  LDS	R18,date+2
    0256 E107      LDI	R16,0x17
    0257 E010      LDI	R17,0
    0258 D3C6      RCALL	_EEPROMwrite
    0259 91200073  LDS	R18,date+1
    025B E105      LDI	R16,0x15
    025C E010      LDI	R17,0
    025D D3C1      RCALL	_EEPROMwrite
(0143) 	}
(0144)    if((date[1]==date[3])&&(date[2]==date[4])&&(date[0]%2==1))
    025E 90200075  LDS	R2,date+3
    0260 90300073  LDS	R3,date+1
    0262 1432      CP	R3,R2
    0263 F4A1      BNE	0x0278
    0264 90200076  LDS	R2,0x76
    0266 90300074  LDS	R3,date+2
    0268 1432      CP	R3,R2
    0269 F471      BNE	0x0278
    026A E012      LDI	R17,2
    026B 91000072  LDS	R16,date
    026D D33F      RCALL	mod8u
    026E 3001      CPI	R16,1
    026F F441      BNE	0x0278
(0145)     {start=1; bee(1000,400); }
    0270 E081      LDI	R24,1
    0271 9380009E  STS	start,R24
    0273 E920      LDI	R18,0x90
    0274 E031      LDI	R19,1
    0275 EE08      LDI	R16,0xE8
    0276 E013      LDI	R17,3
    0277 DE69      RCALL	_bee
(0146)    }
(0147)   } 
(0148)  TCNT1H = 0xF0; //setup
    0278 EF80      LDI	R24,0xF0
    0279 BD8D      OUT	0x2D,R24
(0149)  TCNT1L = 0xBE;
    027A EB8E      LDI	R24,0xBE
    027B BD8C      OUT	0x2C,R24
    027C D386      RCALL	pop_lset
    027D 9518      RETI
(0150) }
(0151) 
(0152) 
(0153) 
(0154) 
(0155) 
(0156) 
(0157) 
(0158) 
(0159) void a(void)           ///*********///
(0160) {
(0161)  tm[3]=date[1]/10; tm[2]=date[1]%10; tm[1]=date[2]/10; tm[0]=date[2]%10;
_a:
    027E E01A      LDI	R17,0xA
    027F 91000073  LDS	R16,date+1
    0281 D32D      RCALL	div8u
    0282 9300006F  STS	tm+3,R16
    0284 E01A      LDI	R17,0xA
    0285 91000073  LDS	R16,date+1
    0287 D325      RCALL	mod8u
    0288 9300006E  STS	tm+2,R16
    028A E01A      LDI	R17,0xA
    028B 91000074  LDS	R16,date+2
    028D D321      RCALL	div8u
    028E 9300006D  STS	tm+1,R16
    0290 E01A      LDI	R17,0xA
    0291 91000074  LDS	R16,date+2
    0293 D319      RCALL	mod8u
    0294 9300006C  STS	tm,R16
(0162)  if(date[1]<10) tm[3]=11;
    0296 91800073  LDS	R24,date+1
    0298 308A      CPI	R24,0xA
    0299 F418      BCC	0x029D
    029A E08B      LDI	R24,0xB
    029B 9380006F  STS	tm+3,R24
(0163)  if(((s%3)==0)&&(win%2==0))  tm[3]=tm[2]=tm[1]=tm[0]=10;
    029D E013      LDI	R17,3
    029E 910000A6  LDS	R16,s
    02A0 D30C      RCALL	mod8u
    02A1 2300      TST	R16
    02A2 F479      BNE	0x02B2
    02A3 E012      LDI	R17,2
    02A4 9100007B  LDS	R16,win
    02A6 D306      RCALL	mod8u
    02A7 2300      TST	R16
    02A8 F449      BNE	0x02B2
    02A9 E08A      LDI	R24,0xA
    02AA 9380006C  STS	tm,R24
    02AC 9380006D  STS	tm+1,R24
    02AE 9380006E  STS	tm+2,R24
    02B0 9380006F  STS	tm+3,R24
(0164) a11;DAT(shu[tm[0]]);del(1000);a10;DAT(0xff);del(5);WDR();
    02B2 9AC2      SBI	0x18,2
    02B3 E680      LDI	R24,0x60
    02B4 E090      LDI	R25,0
    02B5 91E0006C  LDS	R30,tm
    02B7 27FF      CLR	R31
    02B8 0FE8      ADD	R30,R24
    02B9 1FF9      ADC	R31,R25
    02BA 8100      LDD	R16,Z+0
    02BB DD93      RCALL	_DAT
    02BC EE08      LDI	R16,0xE8
    02BD E013      LDI	R17,3
    02BE DDC9      RCALL	_del
    02BF 98C2      CBI	0x18,2
    02C0 EF0F      LDI	R16,0xFF
    02C1 DD8D      RCALL	_DAT
    02C2 E005      LDI	R16,5
    02C3 E010      LDI	R17,0
    02C4 DDC3      RCALL	_del
    02C5 95A8      WDR
(0165) a21;DAT(shu[tm[1]]);del(1000);a20;DAT(0xff);del(5);WDR(); 
    02C6 9AC3      SBI	0x18,3
    02C7 E680      LDI	R24,0x60
    02C8 E090      LDI	R25,0
    02C9 91E0006D  LDS	R30,tm+1
    02CB 27FF      CLR	R31
    02CC 0FE8      ADD	R30,R24
    02CD 1FF9      ADC	R31,R25
    02CE 8100      LDD	R16,Z+0