📄 biaotoum48.lst
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(0132) }
(0133) }
(0134)
(0135)
(0136) void show(uchar n,unit dat)
(0137) {
(0138) uchar i;
(0139) for(i=0;i<4;i++){
0187 2744 CLR R20
0188 C011 RJMP 0x019A
(0140) tm[i]=dat%10;
0189 E02A LDI R18,0xA
018A E030 LDI R19,0
018B 018B MOVW R16,R22
018C D1AF RCALL mod16u
018D E08C LDI R24,0xC
018E E091 LDI R25,1
018F 2FE4 MOV R30,R20
0190 27FF CLR R31
0191 0FE8 ADD R30,R24
0192 1FF9 ADC R31,R25
0193 8300 STD Z+0,R16
(0141) dat/=10;
0194 E02A LDI R18,0xA
0195 E030 LDI R19,0
0196 018B MOVW R16,R22
0197 D1A6 RCALL div16u
0198 01B8 MOVW R22,R16
0199 9543 INC R20
019A 3044 CPI R20,4
019B F368 BCS 0x0189
(0142) }
(0143) i=3;
019C E043 LDI R20,3
019D C009 RJMP 0x01A7
(0144) while(tm[i]==0&&i>0){
(0145) tm[i]=11;
019E E08C LDI R24,0xC
019F E091 LDI R25,1
01A0 2FE4 MOV R30,R20
01A1 27FF CLR R31
01A2 0FE8 ADD R30,R24
01A3 1FF9 ADC R31,R25
01A4 E08B LDI R24,0xB
01A5 8380 STD Z+0,R24
(0146) i--;
01A6 954A DEC R20
01A7 E08C LDI R24,0xC
01A8 E091 LDI R25,1
01A9 2FE4 MOV R30,R20
01AA 27FF CLR R31
01AB 0FE8 ADD R30,R24
01AC 1FF9 ADC R31,R25
01AD 8020 LDD R2,Z+0
01AE 2022 TST R2
01AF F419 BNE 0x01B3
01B0 2422 CLR R2
01B1 1624 CP R2,R20
01B2 F358 BCS 0x019E
(0147) }
(0148) tm[3]=n;
01B3 92A0010F STS tm+3,R10
(0149) A();
01B5 DF37 RCALL _A
01B6 D250 RCALL pop_gset3
01B7 9508 RET
_show4:
i --> R20
x --> R20
dat --> R22
01B8 D25A RCALL push_gset2
01B9 2F42 MOV R20,R18
01BA 01B8 MOVW R22,R16
(0150) }
(0151)
(0152)
(0153)
(0154) void show4(unit dat,uchar x)
(0155) {
(0156) uchar i;
(0157) doudian=x;
01BB 93400131 STS doudian,R20
(0158) for(i=0;i<4;i++){
01BD 2744 CLR R20
01BE C011 RJMP 0x01D0
(0159) tm[i]=dat%10;
01BF E02A LDI R18,0xA
01C0 E030 LDI R19,0
01C1 018B MOVW R16,R22
01C2 D179 RCALL mod16u
01C3 E08C LDI R24,0xC
01C4 E091 LDI R25,1
01C5 2FE4 MOV R30,R20
01C6 27FF CLR R31
01C7 0FE8 ADD R30,R24
01C8 1FF9 ADC R31,R25
01C9 8300 STD Z+0,R16
(0160) dat/=10;
01CA E02A LDI R18,0xA
01CB E030 LDI R19,0
01CC 018B MOVW R16,R22
01CD D170 RCALL div16u
01CE 01B8 MOVW R22,R16
01CF 9543 INC R20
01D0 3044 CPI R20,4
01D1 F368 BCS 0x01BF
(0161) }
(0162) i=3;
01D2 E043 LDI R20,3
01D3 C009 RJMP 0x01DD
(0163) while(tm[i]==0&&i>0)
(0164) {
(0165) tm[i]=11;
01D4 E08C LDI R24,0xC
01D5 E091 LDI R25,1
01D6 2FE4 MOV R30,R20
01D7 27FF CLR R31
01D8 0FE8 ADD R30,R24
01D9 1FF9 ADC R31,R25
01DA E08B LDI R24,0xB
01DB 8380 STD Z+0,R24
(0166) i--;
01DC 954A DEC R20
01DD E08C LDI R24,0xC
01DE E091 LDI R25,1
01DF 2FE4 MOV R30,R20
01E0 27FF CLR R31
01E1 0FE8 ADD R30,R24
01E2 1FF9 ADC R31,R25
01E3 8020 LDD R2,Z+0
01E4 2022 TST R2
01E5 F419 BNE 0x01E9
01E6 2422 CLR R2
01E7 1624 CP R2,R20
01E8 F358 BCS 0x01D4
(0167) }
(0168) A();
01E9 DF03 RCALL _A
01EA D21A RCALL pop_gset2
01EB 9508 RET
_PT100:
Rx --> R10
ii --> R12
dat --> Y+8
01EC D14A RCALL push_arg4
01ED D221 RCALL push_gset4
FILE: D:\ele\AVR\ICC\biaotao\biaotouM48\PT100.h
(0001) #define R 220 // 4 5 6 7
(0002) unit flash RPt100[20]={0,0,0,0,10000,0,11361,35,11940,50,13850,100,17216,190,21202,300,28090,500,31513,700};
(0003)
(0004) unit PT100(ulong dat)
(0005) {
(0006) uchar ii=0;
01EE 24CC CLR R12
(0007) unit Rx;
(0008) Rx=(((1024-dat)*22000)/dat);
01EF 01FE MOVW R30,R28
01F0 8420 LDD R2,Z+8
01F1 8431 LDD R3,Z+9
01F2 8442 LDD R4,Z+10
01F3 8453 LDD R5,Z+11
01F4 E040 LDI R20,0
01F5 E054 LDI R21,4
01F6 E060 LDI R22,0
01F7 E070 LDI R23,0
01F8 1942 SUB R20,R2
01F9 0953 SBC R21,R3
01FA 0964 SBC R22,R4
01FB 0975 SBC R23,R5
01FC EF80 LDI R24,0xF0
01FD E595 LDI R25,0x55
01FE E0A0 LDI R26,0
01FF E0B0 LDI R27,0
0200 937A ST R23,-Y
0201 936A ST R22,-Y
0202 935A ST R21,-Y
0203 934A ST R20,-Y
0204 018C MOVW R16,R24
0205 019D MOVW R18,R26
0206 D1D2 RCALL empy32u
0207 01FE MOVW R30,R28
0208 8420 LDD R2,Z+8
0209 8431 LDD R3,Z+9
020A 8442 LDD R4,Z+10
020B 8453 LDD R5,Z+11
020C 925A ST R5,-Y
020D 924A ST R4,-Y
020E 923A ST R3,-Y
020F 922A ST R2,-Y
0210 D147 RCALL div32u
0211 0158 MOVW R10,R16
0212 C001 RJMP 0x0214
(0009) while(RPt100[2*ii]<=Rx)
(0010) {
(0011) ii++;
0213 94C3 INC R12
0214 E082 LDI R24,2
0215 9D8C MUL R24,R12
0216 2D10 MOV R17,R0
0217 E002 LDI R16,2
0218 0201 MULS R16,R17
0219 01F0 MOVW R30,R0
021A E384 LDI R24,0x34
021B E090 LDI R25,0
021C 0FE8 ADD R30,R24
021D 1FF9 ADC R31,R25
021E 9005 LPM R0,Z+
021F 9014 LPM R1,0(Z)
0220 01F0 MOVW R30,R0
0221 16AE CP R10,R30
0222 06BF CPC R11,R31
0223 F778 BCC 0x0213
(0012) }
(0013) ii<<=1;
0224 0CCC LSL R12
(0014) ii-=2;
0225 2D8C MOV R24,R12
0226 5082 SUBI R24,2
0227 2EC8 MOV R12,R24
(0015) return (((RPt100[ii+3]-RPt100[ii+1])*((Rx-RPt100[ii])/10))/((RPt100[ii+2]-RPt100[ii])/10)+RPt100[ii+1]) ;
0228 E082 LDI R24,2
0229 9D8C MUL R24,R12
022A 0110 MOVW R2,R0
022B E384 LDI R24,0x34
022C E090 LDI R25,0
022D 01F1 MOVW R30,R2
022E 0FE8 ADD R30,R24
022F 1FF9 ADC R31,R25
0230 9045 LPM R4,Z+
0231 9054 LPM R5,0(Z)
0232 E386 LDI R24,0x36
0233 E090 LDI R25,0
0234 01F1 MOVW R30,R2
0235 0FE8 ADD R30,R24
0236 1FF9 ADC R31,R25
0237 9005 LPM R0,Z+
0238 9014 LPM R1,0(Z)
0239 01F0 MOVW R30,R0
023A E38A LDI R24,0x3A
023B E090 LDI R25,0
023C 01D1 MOVW R26,R2
023D 0FA8 ADD R26,R24
023E 1FB9 ADC R27,R25
023F 93FA ST R31,-Y
0240 93EA ST R30,-Y
0241 01FD MOVW R30,R26
0242 91A5 LPM R26,Z+
0243 91B4 LPM R27,0(Z)
0244 91E9 LD R30,Y+
0245 91F9 LD R31,Y+
0246 1BAE SUB R26,R30
0247 0BBF SBC R27,R31
0248 0185 MOVW R16,R10
0249 1904 SUB R16,R4
024A 0915 SBC R17,R5
024B E02A LDI R18,0xA
024C E030 LDI R19,0
024D D0F0 RCALL div16u
024E 0198 MOVW R18,R16
024F 018D MOVW R16,R26
0250 D178 RCALL empy16s
0251 0138 MOVW R6,R16
0252 E388 LDI R24,0x38
0253 E090 LDI R25,0
0254 01F1 MOVW R30,R2
0255 0FE8 ADD R30,R24
0256 1FF9 ADC R31,R25
0257 9105 LPM R16,Z+
0258 9114 LPM R17,0(Z)
0259 1904 SUB R16,R4
025A 0915 SBC R17,R5
025B E02A LDI R18,0xA
025C E030 LDI R19,0
025D D0E0 RCALL div16u
025E 0198 MOVW R18,R16
025F 0183 MOVW R16,R6
0260 D0DD RCALL div16u
0261 0128 MOVW R4,R16
0262 E386 LDI R24,0x36
0263 E090 LDI R25,0
0264 01F1 MOVW R30,R2
0265 0FE8 ADD R30,R24
0266 1FF9 ADC R31,R25
0267 9005 LPM R0,Z+
0268 9014 LPM R1,0(Z)
0269 01F0 MOVW R30,R0
026A 0E4E ADD R4,R30
026B 1E5F ADC R5,R31
026C 0182 MOVW R16,R4
026D D19B RCALL pop_gset4
026E 9624 ADIW R28,4
026F 9508 RET
FILE: D:\ele\AVR\ICC\biaotao\biaotouM48\btm48.c
(0001) #include <iom48v.h>
(0002) #include "bt.h"
(0003) #include "PT100.h"
(0004) #include <macros.h>
(0005) #include <eeprom.h>
(0006)
(0007) #define uchar unsigned char
(0008) #define unit unsigned int
(0009) #define ulong unsigned long
(0010)
(0011)
(0012)
(0013) #define xtal 8
(0014) #define fosc 8000000 //晶振8MHZ
(0015) #define baud 9600 //波特率
(0016)
(0017)
(0018) #define VTest PORTC|=0X80 //测量端口电压
(0019) #define TestIO ((PINB&0X01)==0X01) //测量频率
(0020)
(0021)
(0022) //Watchdog initialize
(0023) // prescale: 16K
(0024) void watchdog_init(void)
(0025) {
(0026) WDR(); //this prevents a timout on enabling
_watchdog_init:
0270 95A8 WDR
(0027) WDTCSR = 0x0B; //WATCHDOG ENABLED - dont forget to issue WDRs
0271 E08B LDI R24,0xB
0272 93800060 STS 0x60,R24
0274 9508 RET
(0028) }
(0029)
(0030)
(0031)
(0032)
(0033) /* 字符输出函数 */
(0034) void putchar(unsigned char c)
(0035) {
_putchar:
c --> R16
0275 C001 RJMP 0x0277
(0036) while (!(UCSR0A&(1<<UDRE0)))WDR();
0276 95A8 WDR
0277 902000C0 LDS R2,0xC0
0279 FE25 SBRS R2,5
027A CFFB RJMP 0x0276
(0037) UDR0=c;
027B 930000C6 STS 0xC6,R16
027D 9508 RET
(0038) // del(200);
(0039) }
(0040)
(0041) //UART0 initialize
(0042) // desired baud rate: 9600
(0043) // actual: baud rate:9615 (0.2%)
(0044) void uart0_init(void)
(0045) {
(0046) UCSR0B = 0x00; //disable while setting baud rate
_uart0_init:
027E 2422 CLR R2
027F 922000C1 STS 0xC1,R2
(0047) UCSR0A = 0x02;
0281 E082 LDI R24,2
0282 938000C0 STS 0xC0,R24
(0048) UCSR0C = 0x06;
0284 E086 LDI R24,6
0285 938000C2 STS 0xC2,R24
(0049) UBRR0L = 0x67; //set baud rate lo
0287 E687 LDI R24,0x67
0288 938000C4 STS 0xC4,R24
(0050) UBRR0H = 0x00; //set baud rate hi
028A 922000C5 STS 0xC5,R2
(0051) UCSR0B = 0x18;
028C E188 LDI R24,0x18
028D 938000C1 STS 0xC1,R24
028F 9508 RET
(0052) }
(0053)
(0054)
(0055) unsigned long adc_rel[8];//AD转换结果
(0056) unsigned char adc_mux;//AD通道
(0057)
(0058) //ADC initialize
(0059) // Cpbversipb time: 3uS
(0060) void adc_init(void)
(0061) {
(0062) ADCSRA = 0x00; //disable adc
_adc_init:
0290 2422 CLR R2
0291 9220007A STS 0x7A,R2
(0063) ADMUX = 0x40; //select adc input 0 00-ref 01-avcc 11-2.56
0293 E480 LDI R24,0x40
0294 9380007C STS 0x7C,R24
(0064) ACSR = 0x80;
0296 E880 LDI R24,0x80
0297 BF80 OUT 0x30,R24
(0065) ADCSRA=(1<<ADEN)|(1<<ADSC)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0) ;//64分频
0298 EC87 LDI R24,0xC7
0299 9380007A STS 0x7A,R24
029B 9508 RET
_cw:
mux --> R20
029C D178 RCALL push_gset1
029D 2F40 MOV R20,R16
(0066) }
(0067)
(0068)
(0069) unit cw(uchar mux) ///*****检测信号*****///
(0070) {
(0071) ADMUX=(1<<REFS0)|(mux&0x0f);
029E 2F84 MOV R24,R20
029F 708F ANDI R24,0xF
02A0 6480 ORI R24,0x40
02A1 9380007C STS 0x7C,R24
(0072) ADCSRA|=0x40;
02A3 9180007A LDS R24,0x7A
02A5 6480 ORI R24,0x40
02A6 9380007A STS 0x7A,R24
(0073) del(200);
02A8 EC08 LDI R16,0xC8
02A9 E010 LDI R17,0
02AA DDF1 RCALL _del
(0074) return(ADC);
02AB 91000078 LDS R16,0x78
02AD 91100079 LDS R17,0x79
02AF D168 RCALL pop_gset1
02B0 9508 RET
_cw1:
a --> Y+1
adc_rel --> R22
i --> R10
mux --> R20
02B1 D15F RCALL push_gset3
02B2 2F40 MOV R20,R16
(0075) }
(0076)
(0077) unit cw1(uchar mux) ///*****检测信号*****///
(0078) {
(0079) unit adc_rel=0,a;
02B3 2766 CLR R22
02B4 2777 CLR R23
(0080) uchar i;
(0081) for(i=0;i<5;i++)
02B5 24AA CLR R10
02B6 C006 RJMP 0x02BD
(0082) {
(0083) adc_rel+=cw(mux);
02B7 2F04 MOV R16,R20
02B8 DFE3 RCALL _cw
02B9 0F60 ADD R22,R16
02BA 1F71 ADC R23,R17
(0084) WDR();
02BB 95A8 WDR
02BC 94A3 INC R10
02BD 2D8A MOV R24,R10
02BE 3085 CPI R24,5
02BF F3B8 BCS 0x02B7
(0085) }
(0086) return (unit)(adc_rel/5);
02C0 E025 LDI R18,5
02C1 E030 LDI R19,0
02C2 018B MOVW R16,R22
02C3 D07A RCALL div16u
02C4 D142 RCALL pop_gset3
02C5 9508 RET
(0087) }
(0088)
(0089)
(0090) //call this routine to initialize all peripherals
(0091) void init_devices(void)
(0092) {
(0093) //stop errant interrupts until set up
(0094) CLI(); //disable all interrupts
_init_devices:
02C6 94F8 BCLR 7
(0095) port_init();
02C7 DD8E RCALL _port_init
(0096) watchdog_init();
02C8 DFA7 RCALL _watchdog_init
(0097) adc_init();
02C9 DFC6 RCALL _adc_init
(0098)
(0099) MCUCR = 0x00;
02CA 2422 CLR R2
02CB BE25 OUT 0x35,R2
(0100) EICRA = 0x00; //extended ext ints
02CC 92200069 STS 0x69,R2
(0101) EIMSK = 0x00;
02CE BA2D OUT 0x1D,R2
(0102)
(0103) TIMSK0 = 0x00; //timer 0 interrupt sources
02CF 9220006E STS 0x6E,R2
(0104) TIMSK1 = 0x00; //timer 1 interrupt sources
02D1 9220006F STS 0x6F,R2
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