📄 clock.rpt
字号:
clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
195 - - - 26 INPUT ^ 0 0 0 1 hourhset0
65 - - - 26 INPUT ^ 0 0 0 1 hourhset1
58 - - - 31 INPUT ^ 0 0 0 1 hourlset0
200 - - - 30 INPUT ^ 0 0 0 1 hourlset1
142 - - B -- INPUT ^ 0 0 0 1 hourlset2
203 - - - 32 INPUT ^ 0 0 0 1 hourlset3
68 - - - 24 INPUT ^ 0 0 0 1 minhset0
196 - - - 27 INPUT ^ 0 0 0 1 minhset1
139 - - B -- INPUT ^ 0 0 0 1 minhset2
26 - - D -- INPUT ^ 0 0 0 1 minlset0
190 - - - 22 INPUT ^ 0 0 0 1 minlset1
140 - - B -- INPUT ^ 0 0 0 1 minlset2
186 - - - 19 INPUT ^ 0 0 0 1 minlset3
128 - - D -- INPUT ^ 0 0 0 1 sechset0
126 - - D -- INPUT ^ 0 0 0 1 sechset1
28 - - D -- INPUT ^ 0 0 0 1 sechset2
80 - - - -- INPUT ^ 0 0 0 1 seclset0
182 - - - -- INPUT ^ 0 0 0 1 seclset1
184 - - - -- INPUT ^ 0 0 0 1 seclset2
183 - - - -- INPUT ^ 0 0 0 1 seclset3
78 - - - -- INPUT G ^ 0 0 0 0 settime
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
204 - - - 33 OUTPUT 0 1 0 0 hourhdis0
206 - - - 34 OUTPUT 0 1 0 0 hourhdis1
12 - - B -- OUTPUT 0 1 0 0 hourldis0
14 - - B -- OUTPUT 0 1 0 0 hourldis1
199 - - - 29 OUTPUT 0 1 0 0 hourldis2
61 - - - 29 OUTPUT 0 1 0 0 hourldis3
13 - - B -- OUTPUT 0 1 0 0 minhdis0
141 - - B -- OUTPUT 0 1 0 0 minhdis1
64 - - - 26 OUTPUT 0 1 0 0 minhdis2
191 - - - 23 OUTPUT 0 1 0 0 minldis0
15 - - B -- OUTPUT 0 1 0 0 minldis1
143 - - B -- OUTPUT 0 1 0 0 minldis2
144 - - B -- OUTPUT 0 1 0 0 minldis3
31 - - D -- OUTPUT 0 1 0 0 sechdis0
25 - - D -- OUTPUT 0 1 0 0 sechdis1
29 - - D -- OUTPUT 0 1 0 0 sechdis2
24 - - C -- OUTPUT 0 1 0 0 secldis0
132 - - C -- OUTPUT 0 1 0 0 secldis1
19 - - C -- OUTPUT 0 1 0 0 secldis2
135 - - C -- OUTPUT 0 1 0 0 secldis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 34 OR2 ! 0 2 0 5 |LPM_ADD_SUB:365|addcore:adder|:59
- 3 - B 36 AND2 0 2 0 1 |LPM_ADD_SUB:563|addcore:adder|:59
- 5 - B 36 OR2 0 4 0 1 |LPM_ADD_SUB:563|addcore:adder|:77
- 2 - C 30 AND2 0 2 0 1 |LPM_ADD_SUB:838|addcore:adder|:59
- 7 - C 30 AND2 0 3 0 1 |LPM_ADD_SUB:838|addcore:adder|:63
- 3 - C 30 DFFE + 1 2 1 1 seclow3 (:43)
- 4 - C 30 DFFE + 1 2 1 2 seclow2 (:44)
- 5 - C 30 DFFE + 1 2 1 3 seclow1 (:45)
- 6 - C 30 DFFE + 1 0 1 4 seclow0 (:46)
- 5 - D 23 DFFE + 1 1 1 2 sechigh2 (:47)
- 1 - D 23 DFFE + 1 1 1 3 sechigh1 (:48)
- 7 - D 23 DFFE + 1 1 1 3 sechigh0 (:49)
- 1 - B 36 DFFE + 1 2 1 3 minlow3 (:50)
- 2 - B 36 DFFE + 1 2 1 3 minlow2 (:51)
- 6 - B 32 DFFE + 1 2 1 4 minlow1 (:52)
- 3 - D 23 DFFE + 1 2 1 4 minlow0 (:53)
- 2 - B 25 DFFE + 1 2 1 6 minhigh2 (:54)
- 5 - B 25 DFFE + 1 3 1 6 minhigh1 (:55)
- 2 - B 32 DFFE + 1 1 1 6 minhigh0 (:56)
- 4 - B 30 DFFE + 1 2 1 3 hourlow3 (:57)
- 2 - B 30 DFFE + 1 2 1 4 hourlow2 (:58)
- 8 - B 34 DFFE + 1 3 1 4 hourlow1 (:59)
- 1 - B 34 DFFE + 1 1 1 4 hourlow0 (:60)
- 6 - B 33 AND2 s 0 4 0 1 hourhigh1~1 (~61~1)
- 7 - B 33 DFFE + 1 2 1 2 hourhigh1 (:61)
- 3 - B 33 DFFE + 1 2 1 3 hourhigh0 (:62)
- 6 - B 25 AND2 s 0 4 0 1 ~219~1
- 4 - B 32 AND2 s 0 2 0 1 ~219~2
- 1 - B 32 AND2 s 0 2 0 1 ~219~3
- 1 - B 30 AND2 s 0 3 0 1 ~219~4
- 6 - B 30 AND2 s 0 4 0 1 ~219~5
- 1 - C 30 OR2 ! 0 4 0 13 :219
- 2 - D 23 OR2 ! 0 3 0 8 :235
- 8 - B 32 OR2 ! 0 4 0 7 :251
- 3 - B 34 AND2 s 0 2 0 1 ~292~1
- 1 - B 33 OR2 ! 0 4 0 4 :292
- 2 - B 33 OR2 s 0 3 0 1 ~311~1
- 5 - B 30 AND2 s ! 0 2 0 1 ~311~2
- 5 - B 32 AND2 s 0 4 0 6 ~501~1
- 4 - B 33 OR2 s 0 4 0 2 ~513~1
- 7 - B 25 OR2 0 4 0 1 :609
- 3 - B 25 OR2 s 0 4 0 1 ~610~1
- 6 - B 36 OR2 0 4 0 1 :726
- 4 - B 36 OR2 0 4 0 1 :732
- 7 - B 32 OR2 0 4 0 1 :738
- 8 - B 25 OR2 0 3 0 1 :750
- 6 - D 23 OR2 0 4 0 1 :884
- 4 - D 23 OR2 0 4 0 1 :890
- 4 - B 25 OR2 s 0 4 0 1 ~932~1
- 3 - B 32 AND2 s ! 0 3 0 6 ~938~1
- 7 - B 30 OR2 s 0 4 0 1 ~944~1
- 3 - B 30 OR2 s 0 3 0 1 ~950~1
- 4 - B 34 OR2 s 0 4 0 1 ~956~1
- 1 - B 25 AND2 s ! 0 4 0 7 ~962~1
- 5 - B 33 OR2 s 0 4 0 1 ~968~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 23/144( 15%) 0/ 72( 0%) 13/ 72( 18%) 3/16( 18%) 7/16( 43%) 0/16( 0%)
C: 2/144( 1%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 5/144( 3%) 0/ 72( 0%) 3/ 72( 4%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
30: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
Device-Specific Information: e:\eda\clock.rpt
clock
** EQUATIONS **
clk : INPUT;
hourhset0 : INPUT;
hourhset1 : INPUT;
hourlset0 : INPUT;
hourlset1 : INPUT;
hourlset2 : INPUT;
hourlset3 : INPUT;
minhset0 : INPUT;
minhset1 : INPUT;
minhset2 : INPUT;
minlset0 : INPUT;
minlset1 : INPUT;
minlset2 : INPUT;
minlset3 : INPUT;
sechset0 : INPUT;
sechset1 : INPUT;
sechset2 : INPUT;
seclset0 : INPUT;
seclset1 : INPUT;
seclset2 : INPUT;
seclset3 : INPUT;
settime : INPUT;
-- Node name is 'hourhdis0'
-- Equation name is 'hourhdis0', type is output
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