kand2.vhd

来自「maxplus2变得电子钟程序/// /// /////」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY kand2 IS
  PORT(A,B:IN std_logic;
         C:OUT std_logic);
END kand2;                 -----------------二输入与门
ARCHITECTURE kand2_arc OF kand2 IS
BEGIN
  C<=A AND B;
END kand2_arc;