control.rpt

maxplus2变得电子钟程序/// /// /////

         # !hourlow3
         # !hourlow0;

-- Node name is ':746' 
-- Equation name is '_LC5_F25', type is buried 
_LC5_F25 = LCELL( _EQ036);
  _EQ036 = !minlow3
         # !minlow0 & !minlow1 & !minlow2;

-- Node name is ':971' 
-- Equation name is '_LC5_F19', type is buried 
_LC5_F19 = LCELL( _EQ037);
  _EQ037 = !seclow3
         # !seclow0 & !seclow1 & !seclow2;

-- Node name is '~1108~1' 
-- Equation name is '~1108~1', location is LC2_F19, type is buried.
-- synthesized logic cell 
_LC2_F19 = LCELL( _EQ038);
  _EQ038 =  seclow0 &  seclow1 &  seclow2
         #  seclow2 &  seclow3
         #  seclow1 &  seclow3;

-- Node name is '~1108~2' 
-- Equation name is '~1108~2', location is LC3_F19, type is buried.
-- synthesized logic cell 
_LC3_F19 = LCELL( _EQ039);
  _EQ039 =  _LC5_F19 & !seclow1
         #  _LC5_F19 & !seclow0
         #  _LC5_F19 & !seclow2;

-- Node name is '~1129~1' 
-- Equation name is '~1129~1', location is LC8_F35, type is buried.
-- synthesized logic cell 
_LC8_F35 = LCELL( _EQ040);
  _EQ040 =  _LC5_F19 & !_LC6_F35
         #  seclow3
         # !_LC1_F24;

-- Node name is '~1150~1' 
-- Equation name is '~1150~1', location is LC4_F35, type is buried.
-- synthesized logic cell 
_LC4_F35 = LCELL( _EQ041);
  _EQ041 =  seclow3
         # !_LC1_F24
         #  _LC5_F19 & !seclow0;

-- Node name is '~1180~1' 
-- Equation name is '~1180~1', location is LC7_F24, type is buried.
-- synthesized logic cell 
_LC7_F24 = LCELL( _EQ042);
  _EQ042 =  adjust~3 &  sechigh0 &  sechigh1
         # !sechigh0 &  sechigh2
         #  sechigh1 &  sechigh2
         # !adjust~3 &  sechigh2;

-- Node name is '~1186~1' 
-- Equation name is '~1186~1', location is LC2_F24, type is buried.
-- synthesized logic cell 
_LC2_F24 = LCELL( _EQ043);
  _EQ043 = !adjust~4 & !adjust~5 &  _LC7_F24
         #  adjust~4 &  sechigh2
         #  adjust~5 &  sechigh2;

-- Node name is '~1255~1' 
-- Equation name is '~1255~1', location is LC7_F25, type is buried.
-- synthesized logic cell 
_LC7_F25 = LCELL( _EQ044);
  _EQ044 =  _LC5_F25 & !minlow1
         #  _LC5_F25 & !minlow0
         #  _LC5_F25 & !minlow2;

-- Node name is '~1255~2' 
-- Equation name is '~1255~2', location is LC8_F25, type is buried.
-- synthesized logic cell 
_LC8_F25 = LCELL( _EQ045);
  _EQ045 =  minlow0 &  minlow1 &  minlow2
         #  minlow2 &  minlow3
         #  minlow1 &  minlow3;

-- Node name is '~1276~1' 
-- Equation name is '~1276~1', location is LC7_F27, type is buried.
-- synthesized logic cell 
_LC7_F27 = LCELL( _EQ046);
  _EQ046 =  _LC5_F25 & !_LC5_F27
         #  minlow3
         # !_LC3_F25;

-- Node name is '~1297~1' 
-- Equation name is '~1297~1', location is LC4_F27, type is buried.
-- synthesized logic cell 
_LC4_F27 = LCELL( _EQ047);
  _EQ047 =  minlow3
         # !_LC3_F25
         #  _LC5_F25 & !minlow0;

-- Node name is '~1333~1' 
-- Equation name is '~1333~1', location is LC6_F33, type is buried.
-- synthesized logic cell 
_LC6_F33 = LCELL( _EQ048);
  _EQ048 =  adjust~5 &  minhigh0 &  minhigh1
         # !minhigh0 &  minhigh2
         #  minhigh1 &  minhigh2
         # !adjust~5 &  minhigh2;

-- Node name is '~1402~1' 
-- Equation name is '~1402~1', location is LC3_D31, type is buried.
-- synthesized logic cell 
_LC3_D31 = LCELL( _EQ049);
  _EQ049 =  hourlow0 &  hourlow1 &  hourlow2
         #  hourlow2 &  hourlow3
         #  hourlow1 &  hourlow3;

-- Node name is '~1402~2' 
-- Equation name is '~1402~2', location is LC7_D20, type is buried.
-- synthesized logic cell 
_LC7_D20 = LCELL( _EQ050);
  _EQ050 = !hourlow0 & !hourlow1 & !hourlow2
         # !hourlow1 & !hourlow3
         # !hourlow0 & !hourlow3
         # !hourlow2 & !hourlow3;

-- Node name is '~1402~3' 
-- Equation name is '~1402~3', location is LC8_D20, type is buried.
-- synthesized logic cell 
_LC8_D20 = LCELL( _EQ051);
  _EQ051 =  hourhigh1 &  hourlow3
         #  hourlow3 & !_LC4_D20
         #  hourlow3 &  _LC7_D20;

-- Node name is '~1423~1' 
-- Equation name is '~1423~1', location is LC2_D23, type is buried.
-- synthesized logic cell 
_LC2_D23 = LCELL( _EQ052);
  _EQ052 =  hourlow0 &  hourlow1 &  _LC4_D20;

-- Node name is '~1423~2' 
-- Equation name is '~1423~2', location is LC3_D23, type is buried.
-- synthesized logic cell 
_LC3_D23 = LCELL( _EQ053);
  _EQ053 = !hourhigh1 & !hourlow2 &  _LC5_D23
         #  hourhigh1 & !_LC2_D31;

-- Node name is '~1423~3' 
-- Equation name is '~1423~3', location is LC7_D23, type is buried.
-- synthesized logic cell 
_LC7_D23 = LCELL( _EQ054);
  _EQ054 =  hourhigh0 &  hourhigh1
         #  hourhigh1 &  hourlow1
         #  hourhigh1 &  hourlow0;

-- Node name is '~1423~4' 
-- Equation name is '~1423~4', location is LC8_D23, type is buried.
-- synthesized logic cell 
_LC8_D23 = LCELL( _EQ055);
  _EQ055 =  _LC6_D23
         #  _LC7_D23
         #  hourlow3
         # !_LC4_D20;

-- Node name is '~1444~1' 
-- Equation name is '~1444~1', location is LC7_D31, type is buried.
-- synthesized logic cell 
_LC7_D31 = LCELL( _EQ056);
  _EQ056 =  hourhigh1 & !hourlow0
         #  hourhigh1 &  _LC2_D31
         # !hourhigh1 &  hourlow3;

-- Node name is '~1444~2' 
-- Equation name is '~1444~2', location is LC8_D31, type is buried.
-- synthesized logic cell 
_LC8_D31 = LCELL( _EQ057);
  _EQ057 = !hourlow0 &  _LC5_D23
         #  _LC7_D31
         # !_LC4_D20;

-- Node name is '~1465~1' 
-- Equation name is '~1465~1', location is LC4_D20, type is buried.
-- synthesized logic cell 
!_LC4_D20 = _LC4_D20~NOT;
_LC4_D20~NOT = LCELL( _EQ058);
  _EQ058 =  adjust~7
         # !adjust~6;

-- Node name is '~1465~2' 
-- Equation name is '~1465~2', location is LC2_D31, type is buried.
-- synthesized logic cell 
_LC2_D31 = LCELL( _EQ059);
  _EQ059 =  hourhigh0
         #  hourlow3
         #  hourlow2;

-- Node name is '~1465~3' 
-- Equation name is '~1465~3', location is LC1_D31, type is buried.
-- synthesized logic cell 
_LC1_D31 = LCELL( _EQ060);
  _EQ060 = !hourhigh1 &  _LC4_D20 &  _LC5_D23
         #  hourhigh1 & !_LC2_D31 &  _LC4_D20;

-- Node name is '~1465~4' 
-- Equation name is '~1465~4', location is LC5_D31, type is buried.
-- synthesized logic cell 
_LC5_D31 = LCELL( _EQ061);
  _EQ061 =  hourhigh1 &  _LC2_D31
         # !hourhigh1 &  hourlow3 & !_LC4_D23;



Project Information                                         e:\eda\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,944K