📄 control.rpt
字号:
control
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT G ^ 0 0 0 0 begand
79 - - - -- INPUT G ^ 0 0 0 0 enter
183 - - - -- INPUT G ^ 0 0 0 0 keyup
78 - - - -- INPUT G ^ 0 0 0 0 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\control.rpt
control
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - D -- OUTPUT 0 1 0 0 hourhset0
27 - - D -- OUTPUT 0 1 0 0 hourhset1
28 - - D -- OUTPUT 0 1 0 0 hourlset0
30 - - D -- OUTPUT 0 1 0 0 hourlset1
25 - - D -- OUTPUT 0 1 0 0 hourlset2
26 - - D -- OUTPUT 0 1 0 0 hourlset3
206 - - - 34 OUTPUT 0 1 0 0 minhset0
205 - - - 34 OUTPUT 0 1 0 0 minhset1
45 - - F -- OUTPUT 0 1 0 0 minhset2
112 - - F -- OUTPUT 0 1 0 0 minlset0
111 - - F -- OUTPUT 0 1 0 0 minlset1
115 - - F -- OUTPUT 0 1 0 0 minlset2
114 - - F -- OUTPUT 0 1 0 0 minlset3
46 - - F -- OUTPUT 0 1 0 0 sechset0
191 - - - 23 OUTPUT 0 1 0 0 sechset1
75 - - - 19 OUTPUT 0 1 0 0 sechset2
47 - - F -- OUTPUT 0 1 0 0 seclset0
44 - - F -- OUTPUT 0 1 0 0 seclset1
113 - - F -- OUTPUT 0 1 0 0 seclset2
116 - - F -- OUTPUT 0 1 0 0 seclset3
7 - - A -- OUTPUT 0 1 0 0 settime
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\control.rpt
control
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - F 25 DFFE + 0 0 0 1 adjust~1
- 6 - F 24 DFFE + 0 1 0 2 adjust~2
- 4 - F 24 DFFE + 0 1 0 4 adjust~3
- 1 - F 36 DFFE + 0 1 0 5 adjust~4
- 2 - F 25 DFFE + 0 1 0 6 adjust~5
- 1 - D 20 DFFE + 0 1 0 7 adjust~6
- 2 - F 35 OR2 s 0 4 0 1 adjust~7~2
- 1 - F 33 AND2 s 0 3 0 2 adjust~7~3
- 1 - F 24 AND2 s 0 4 0 5 adjust~7~4
- 3 - F 35 AND2 s 0 2 0 3 adjust~7~5
- 5 - F 24 OR2 s ! 0 3 0 2 adjust~7~6
- 1 - F 27 OR2 s 0 4 0 1 adjust~7~7
- 3 - F 25 AND2 s 0 4 0 5 adjust~7~8
- 2 - F 27 AND2 s 0 2 0 3 adjust~7~9
- 5 - F 33 OR2 s ! 0 3 0 2 adjust~7~10
- 6 - D 23 OR2 s 0 4 0 1 adjust~7~11
- 1 - F 25 DFFE + 0 2 0 9 adjust~7
- 5 - F 27 AND2 0 2 0 2 |LPM_ADD_SUB:789|addcore:adder|:59
- 6 - F 35 OR2 ! 0 2 0 2 |LPM_ADD_SUB:1014|addcore:adder|:59
- 1 - A 21 DFFE + 0 0 1 0 setmark (:26)
- 3 - D 20 DFFE + 0 2 1 9 hourhigh1 (:27)
- 5 - D 20 DFFE + 0 2 1 3 hourhigh0 (:28)
- 2 - D 20 DFFE + 0 4 1 9 hourlow3 (:29)
- 1 - D 23 DFFE + 0 3 1 6 hourlow2 (:30)
- 6 - D 31 DFFE + 0 3 1 7 hourlow1 (:31)
- 4 - D 31 DFFE + 0 3 1 10 hourlow0 (:32)
- 3 - F 33 DFFE + 0 3 1 3 minhigh2 (:33)
- 4 - F 33 DFFE + 0 3 1 2 minhigh1 (:34)
- 2 - F 33 DFFE + 0 3 1 2 minhigh0 (:35)
- 4 - F 25 DFFE + 0 3 1 5 minlow3 (:36)
- 3 - F 27 DFFE + 0 3 1 4 minlow2 (:37)
- 8 - F 27 DFFE + 0 3 1 5 minlow1 (:38)
- 6 - F 27 DFFE + 0 3 1 7 minlow0 (:39)
- 6 - D 20 DFFE + 0 3 1 4 sechigh2 (:40)
- 3 - F 24 DFFE + 0 3 1 2 sechigh1 (:41)
- 8 - F 24 DFFE + 0 3 1 2 sechigh0 (:42)
- 1 - F 19 DFFE + 0 3 1 5 seclow3 (:43)
- 5 - F 35 DFFE + 0 3 1 4 seclow2 (:44)
- 1 - F 35 DFFE + 0 3 1 5 seclow1 (:45)
- 7 - F 35 DFFE + 0 3 1 7 seclow0 (:46)
- 5 - D 23 OR2 0 4 0 4 :345
- 4 - D 23 OR2 ! 0 4 0 1 :366
- 5 - F 25 OR2 0 4 0 4 :746
- 5 - F 19 OR2 0 4 0 4 :971
- 2 - F 19 OR2 s 0 4 0 1 ~1108~1
- 3 - F 19 OR2 s 0 4 0 1 ~1108~2
- 8 - F 35 OR2 s 0 4 0 1 ~1129~1
- 4 - F 35 OR2 s 0 4 0 1 ~1150~1
- 7 - F 24 OR2 s 0 4 0 1 ~1180~1
- 2 - F 24 OR2 s 0 4 0 1 ~1186~1
- 7 - F 25 OR2 s 0 4 0 1 ~1255~1
- 8 - F 25 OR2 s 0 4 0 1 ~1255~2
- 7 - F 27 OR2 s 0 4 0 1 ~1276~1
- 4 - F 27 OR2 s 0 4 0 1 ~1297~1
- 6 - F 33 OR2 s 0 4 0 1 ~1333~1
- 3 - D 31 OR2 s 0 4 0 1 ~1402~1
- 7 - D 20 OR2 s 0 4 0 1 ~1402~2
- 8 - D 20 OR2 s 0 4 0 1 ~1402~3
- 2 - D 23 AND2 s 0 3 0 1 ~1423~1
- 3 - D 23 OR2 s 0 4 0 1 ~1423~2
- 7 - D 23 OR2 s 0 4 0 1 ~1423~3
- 8 - D 23 OR2 s 0 4 0 1 ~1423~4
- 7 - D 31 OR2 s 0 4 0 1 ~1444~1
- 8 - D 31 OR2 s 0 4 0 1 ~1444~2
- 4 - D 20 OR2 s ! 0 2 0 7 ~1465~1
- 2 - D 31 OR2 s 0 3 0 4 ~1465~2
- 1 - D 31 OR2 s 0 4 0 2 ~1465~3
- 5 - D 31 OR2 s 0 4 0 1 ~1465~4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\control.rpt
control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 11/144( 7%) 0/ 72( 0%) 6/ 72( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 15/144( 10%) 0/ 72( 0%) 8/ 72( 11%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 keyup
INPUT 7 enter
INPUT 1 begand
Device-Specific Information: e:\eda\control.rpt
control
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 28 reset
Device-Specific Information: e:\eda\control.rpt
control
** EQUATIONS **
begand : INPUT;
enter : INPUT;
keyup : INPUT;
reset : INPUT;
-- Node name is 'adjust~1'
-- Equation name is 'adjust~1', location is LC6_F25, type is buried.
adjust~1 = DFFE( VCC, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~2'
-- Equation name is 'adjust~2', location is LC6_F24, type is buried.
adjust~2 = DFFE( adjust~3, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~3'
-- Equation name is 'adjust~3', location is LC4_F24, type is buried.
adjust~3 = DFFE( adjust~4, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~4'
-- Equation name is 'adjust~4', location is LC1_F36, type is buried.
adjust~4 = DFFE( adjust~5, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~5'
-- Equation name is 'adjust~5', location is LC2_F25, type is buried.
adjust~5 = DFFE( adjust~6, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~6'
-- Equation name is 'adjust~6', location is LC1_D20, type is buried.
adjust~6 = DFFE( adjust~7, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjust~7~2'
-- Equation name is 'adjust~7~2', location is LC2_F35, type is buried.
-- synthesized logic cell
_LC2_F35 = LCELL( _EQ001);
_EQ001 = seclow2 & seclow3
# seclow1 & seclow3
# !seclow0 & seclow3;
-- Node name is 'adjust~7~3'
-- Equation name is 'adjust~7~3', location is LC1_F33, type is buried.
-- synthesized logic cell
_LC1_F33 = LCELL( _EQ002);
_EQ002 = !adjust~5 & !adjust~6 & !adjust~7;
-- Node name is 'adjust~7~4'
-- Equation name is 'adjust~7~4', location is LC1_F24, type is buried.
-- synthesized logic cell
_LC1_F24 = LCELL( _EQ003);
_EQ003 = adjust~2 & !adjust~3 & !adjust~4 & _LC1_F33;
-- Node name is 'adjust~7~5'
-- Equation name is 'adjust~7~5', location is LC3_F35, type is buried.
-- synthesized logic cell
_LC3_F35 = LCELL( _EQ004);
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