knand2.vhd

来自「maxplus2变得电子钟程序/// /// /////」· VHDL 代码 · 共 11 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY knand2 IS
  PORT(A,B:IN std_logic;
         C:OUT std_logic);
END knand2;                  ------------------二输入与非门
ARCHITECTURE knand2_arc OF knand2 IS
BEGIN
  C<=NOT(A AND B);
END knand2_arc;