ring.vhd
来自「maxplus2变得电子钟程序/// /// /////」· VHDL 代码 · 共 116 行
VHD
116 行
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ring IS
PORT( reset: IN STD_LOGIC;
alarm: OUT STD_LOGIC;--drive singal to the bell
hourhdis: IN INTEGER RANGE 0 TO 2;
--time informaton received from module of "clock"
hourldis:IN INTEGER RANGE 0 TO 9;
minhdis: IN INTEGER RANGE 0 TO 5;
minldis: IN INTEGER RANGE 0 TO 9;
sechdis: IN INTEGER RANGE 0 TO 5;
secldis: IN INTEGER RANGE 0 TO 9;
alarmlo:IN STD_LOGIC);
END ring;
ARCHITECTURE ring_archi OF ring IS
CONSTANT RT:INTEGER:=10;
CONSTANT STOP:INTEGER:=5;
SIGNAL alarmlock:STD_LOGIC;
BEGIN
alarmlocking: --set the ring to make sure if it can work
PROCESS(alarmlo,reset)
BEGIN
if reset='1' then
alarmlock<='0';
elsif alarmlo='1' and alarmlo'event then
if alarmlock='1' then
alarmlock<='0';
else alarmlock<='1';
end if;
end if;
END PROCESS;
Ring:
--set the time for ring
PROCESS(secldis)
VARIABLE cnt:INTEGER;
BEGIN
cnt:=sechdis*10+secldis;
if reset='1' then
alarm<='0';
elsif (hourhdis=0 and hourldis=6 and minhdis=0 and minldis =0 and
sechdis<3)
OR
(hourhdis=2 and hourldis=2 and minhdis=3 and minldis =0 and
sechdis<3) then
if cnt<RT then
alarm<='1';
elsif cnt>=RT and cnt<(STOP+RT) then
alarm<='0';
elsif cnt<2*RT+STOP then
alarm<='1';
else
alarm<='0';
end if;
else
if alarmlock='1' and cnt<5 and
((hourhdis=0 and hourldis=0 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=1 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=2 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=3 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=4 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=5 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=6 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=7 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=8 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=0 and hourldis=9 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=0 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=1 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=2 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=3 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=4 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=5 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=6 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=7 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=8 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=1 and hourldis=9 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=2 and hourldis=0 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=2 and hourldis=1 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=2 and hourldis=2 and minhdis=0 and minldis =0 and sechdis=0)
OR
(hourhdis=2 and hourldis=3 and minhdis=0 and minldis =0 and sechdis=0)) then
alarm<='1';
else
alarm<='0';
end if;
end if;
END PROCESS;
END ring_archi;
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