clock.vhd

maxplus2变得电子钟程序/// /// /////

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clock IS
    port(clk: IN STD_LOGIC;   --system clock ,  1HZ
         settime:  IN STD_LOGIC;  --received from "control" module
         hourhset: IN  INTEGER RANGE 0 TO 2;  
                         --	received adjusted time from "control" module
         hourlset: IN  INTEGER RANGE 0 TO 9; 
         minhset: IN  INTEGER RANGE 0 TO 5;
         minlset: IN  INTEGER RANGE 0 TO 9;
         sechset: IN  INTEGER RANGE 0 TO 5;
         seclset: IN  INTEGER RANGE 0 TO 9;
         hourhdis: OUT  INTEGER RANGE 0 to 2;  
                         --	tine to be sent to "display"module         
         hourldis: OUT  INTEGER RANGE 0 to 9; 
         minhdis: OUT  INTEGER RANGE 0 to 5;
         minldis: OUT  INTEGER RANGE 0 to 9;
         sechdis: OUT  INTEGER RANGE 0 to 5;
         secldis: OUT  INTEGER RANGE 0 to 9);
END clock;
ARCHITECTURE clock_archi OF clock IS
    SIGNAL  seclow,minlow ,hourlow: INTEGER RANGE 0 TO 9;
    SIGNAL  sechigh,minhigh:  INTEGER RANGE 0 TO 5;
    SIGNAL  hourhigh:  INTEGER RANGE 0 TO 2;
    BEGIN
       secldis<=seclow;
       sechdis<=sechigh;
       minldis<=minlow;
       minhdis<=minhigh;
       hourldis<=hourlow;
       hourhdis<=hourhigh;
normal_run:
        --this process complete normal time running
      PROCESS(clk,settime)
         BEGIN  
             if settime='1' then 
                seclow<=seclset;
                sechigh<=sechset;
                minlow<=minlset;
                minhigh<=minhset;
                hourlow<=hourlset;
                hourhigh<=hourhset;
             else
                if clk='1' and clk'event then
                   if seclow=9 then
                      seclow<=0;
                      if sechigh=5 then
                         sechigh<=0;
                        if minlow=9 then
                           minlow<=0;
                          if minhigh=5 then
                            minhigh<=0;
                             if hourlow=9 then
                              hourlow<=0;
                               hourhigh<=hourhigh+1;
                             elsif hourlow=3 and hourhigh=2 then
                               hourhigh<=0;
                               hourlow<=0;
                            else 
                                hourlow<=hourlow+1;
                             end if;
                         else
                            minhigh<=minhigh+1;
                          end if;
                       else
                         minlow<=minlow+1;
                       end if;
                    else
                       sechigh<=sechigh+1;
                    end if;
                 else
                     seclow<=seclow+1;
                end if;
               end if;
             end if;
           END PROCESS;
       END clock_archi;