ksy.vhd

来自「maxplus2变得电子钟程序/// /// /////」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY ksy IS
  PORT(A,B:IN std_logic;
         C:OUT std_logic);
END ksy;                       ----------  同步消抖电路
ARCHITECTURE ksy_arc OF ksy IS
  COMPONENT kand2 IS
    PORT(A,B:IN std_logic;
           C:OUT std_logic);
  END COMPONENT;               -----------    二输入与门
  COMPONENT knand2 IS
    PORT(A,B:IN std_logic;
           C:OUT std_logic);
  END COMPONENT;               -----------    二输入与非们
  COMPONENT kdf IS
    PORT(A,B:IN std_logic;
         C,D:OUT std_logic);
  END COMPONENT;              -----------     D触发器
  SIGNAL T1,T2,T3,T4,T5,T6,T7:std_logic;
BEGIN
  T7<= NOT A;
  U0:knand2 PORT MAP(T7,T1,T2);
  U1:knand2 PORT MAP(T2,T3,T1);
  U2:kdf PORT MAP(T2,B,T4,T3);
  U3:kdf PORT MAP(T4,B,T6,T5);
  U4:kand2 PORT MAP(T4,T5,C);
END ksy_arc;