📄 eclock.rpt
字号:
- 6 - A 36 OR2 s 0 4 0 1 |CONTROL:2|~1255~2
- 7 - A 36 OR2 s 0 4 0 1 |CONTROL:2|~1255~3
- 5 - A 36 OR2 s 0 4 0 1 |CONTROL:2|~1276~1
- 4 - A 35 OR2 s 0 4 0 1 |CONTROL:2|~1297~1
- 5 - A 29 OR2 s 0 4 0 1 |CONTROL:2|~1333~1
- 3 - A 29 OR2 s 0 3 0 2 |CONTROL:2|~1360~1
- 5 - A 31 OR2 s 0 4 0 1 |CONTROL:2|~1402~1
- 4 - A 27 AND2 s 0 2 0 8 |CONTROL:2|~1402~2
- 5 - A 20 OR2 s 0 4 0 1 |CONTROL:2|~1402~3
- 6 - A 31 OR2 s 0 4 0 1 |CONTROL:2|~1402~4
- 3 - A 20 OR2 s 0 4 0 1 |CONTROL:2|~1423~1
- 6 - A 20 AND2 s 0 4 0 1 |CONTROL:2|~1423~2
- 7 - A 31 OR2 s 0 3 0 1 |CONTROL:2|~1423~3
- 3 - A 31 OR2 s 0 4 0 1 |CONTROL:2|~1423~4
- 2 - A 31 AND2 s ! 0 3 0 4 |CONTROL:2|~1444~1
- 8 - A 26 OR2 s 0 3 0 2 |CONTROL:2|~1444~2
- 4 - A 26 OR2 s 0 4 0 1 |CONTROL:2|~1444~3
- 7 - A 26 OR2 s 0 4 0 1 |CONTROL:2|~1444~4
- 1 - A 26 OR2 s 0 4 0 1 |CONTROL:2|~1465~1
- 7 - A 23 DFFE + 0 3 0 5 |DISPLAY:3|cursta2 (|DISPLAY:3|:37)
- 1 - A 24 DFFE + 0 4 0 6 |DISPLAY:3|cursta1 (|DISPLAY:3|:38)
- 6 - A 23 DFFE + 0 2 0 6 |DISPLAY:3|cursta0 (|DISPLAY:3|:39)
- 7 - A 17 AND2 0 4 0 1 |DISPLAY:3|:1286
- 6 - A 25 AND2 s 0 2 0 1 |DISPLAY:3|~1298~1
- 1 - A 28 OR2 ! 0 4 0 1 |DISPLAY:3|:1334
- 7 - A 24 OR2 ! 0 4 0 1 |DISPLAY:3|:1346
- 5 - A 17 AND2 0 4 0 4 |DISPLAY:3|:1370
- 6 - A 12 OR2 0 4 0 1 |DISPLAY:3|:1435
- 3 - A 17 OR2 0 4 0 1 |DISPLAY:3|:1495
- 8 - A 17 OR2 0 4 0 1 |DISPLAY:3|:1553
- 6 - A 17 OR2 0 4 0 1 |DISPLAY:3|:1585
- 8 - A 13 OR2 s 0 2 0 5 |DISPLAY:3|~1849~1
- 1 - A 12 AND2 0 3 0 3 |DISPLAY:3|:1859
- 3 - A 12 OR2 0 3 0 1 |DISPLAY:3|:1922
- 4 - A 13 OR2 0 3 0 1 |DISPLAY:3|:1984
- 2 - A 11 OR2 0 3 0 1 |DISPLAY:3|:2074
- 2 - A 08 OR2 ! 0 4 0 2 |DISPLAY:3|:2344
- 5 - A 08 OR2 ! 0 4 0 1 |DISPLAY:3|:2356
- 4 - A 08 AND2 0 4 0 5 |DISPLAY:3|:2368
- 6 - A 08 OR2 s 0 4 0 1 |DISPLAY:3|~2433~1
- 3 - A 09 OR2 0 4 0 1 |DISPLAY:3|:2491
- 8 - A 32 OR2 s ! 0 4 0 1 |DISPLAY:3|~2551~1
- 1 - A 09 OR2 0 4 0 1 |DISPLAY:3|:2551
- 2 - A 03 OR2 0 4 0 1 |DISPLAY:3|:2583
- 2 - A 25 AND2 0 2 0 3 |DISPLAY:3|:2827
- 8 - A 05 AND2 0 3 0 4 |DISPLAY:3|:2837
- 2 - A 05 AND2 0 3 0 7 |DISPLAY:3|:2857
- 4 - A 05 OR2 0 4 0 1 |DISPLAY:3|:2920
- 1 - A 05 OR2 0 3 0 1 |DISPLAY:3|:2982
- 2 - A 04 OR2 ! 0 3 0 2 |DISPLAY:3|:3030
- 8 - A 18 OR2 s 0 4 0 1 |DISPLAY:3|~3040~1
- 6 - A 04 OR2 ! 0 3 0 3 |DISPLAY:3|:3072
- 5 - A 10 OR2 ! 0 4 0 2 |DISPLAY:3|:3342
- 8 - A 10 OR2 ! 0 4 0 2 |DISPLAY:3|:3354
- 6 - A 10 AND2 0 4 0 2 |DISPLAY:3|:3366
- 5 - A 02 OR2 0 4 0 1 |DISPLAY:3|:3429
- 1 - A 03 OR2 0 4 0 1 |DISPLAY:3|:3489
- 6 - A 18 OR2 0 4 0 1 |DISPLAY:3|:3549
- 3 - A 03 OR2 0 4 0 1 |DISPLAY:3|:3579
- 5 - A 23 AND2 0 3 0 8 |DISPLAY:3|:3606
- 4 - A 23 AND2 0 3 0 11 |DISPLAY:3|:3616
- 2 - A 23 AND2 0 3 0 14 |DISPLAY:3|:3626
- 1 - A 23 OR2 ! 0 3 0 11 |DISPLAY:3|:3636
- 3 - A 23 AND2 0 3 0 11 |DISPLAY:3|:3646
- 6 - A 21 AND2 0 4 1 0 |DISPLAY:3|:3651
- 6 - A 24 OR2 0 4 1 0 |DISPLAY:3|:3669
- 6 - A 05 OR2 0 4 0 1 |DISPLAY:3|:3709
- 7 - A 05 OR2 s 0 3 0 2 |DISPLAY:3|~3710~1
- 4 - A 10 OR2 s 0 4 0 1 |DISPLAY:3|~3711~1
- 4 - A 09 OR2 s 0 4 0 1 |DISPLAY:3|~3713~1
- 4 - A 11 OR2 0 4 0 1 |DISPLAY:3|:3716
- 6 - A 09 OR2 0 4 0 1 |DISPLAY:3|:3717
- 7 - A 09 OR2 0 4 0 1 |DISPLAY:3|:3718
- 1 - A 17 OR2 s 0 4 0 1 |DISPLAY:3|~3719~1
- 2 - A 09 OR2 0 3 1 0 |DISPLAY:3|:3721
- 7 - A 08 OR2 0 4 0 1 |DISPLAY:3|:3731
- 2 - A 12 OR2 0 4 0 1 |DISPLAY:3|:3732
- 5 - A 12 OR2 0 4 0 1 |DISPLAY:3|:3733
- 7 - A 12 OR2 0 4 0 1 |DISPLAY:3|:3736
- 4 - A 12 OR2 0 4 1 0 |DISPLAY:3|:3739
- 1 - A 08 OR2 s 0 4 0 1 |DISPLAY:3|~3757~1
- 3 - A 08 OR2 s 0 4 0 1 |DISPLAY:3|~3757~2
- 7 - A 10 OR2 s 0 4 0 1 |DISPLAY:3|~3757~3
- 2 - A 10 OR2 s 0 4 0 1 |DISPLAY:3|~3757~4
- 5 - A 05 OR2 s 0 3 0 1 |DISPLAY:3|~3757~5
- 1 - A 11 OR2 s 0 4 0 1 |DISPLAY:3|~3757~6
- 3 - A 11 OR2 s 0 3 0 1 |DISPLAY:3|~3757~7
- 7 - A 11 OR2 s 0 4 0 1 |DISPLAY:3|~3757~8
- 2 - A 17 OR2 s 0 4 0 1 |DISPLAY:3|~3757~9
- 8 - A 11 OR2 s 0 4 0 1 |DISPLAY:3|~3757~10
- 6 - A 11 OR2 0 3 1 0 |DISPLAY:3|:3757
- 3 - A 05 OR2 0 4 0 1 |DISPLAY:3|:3763
- 5 - A 09 OR2 0 3 0 1 |DISPLAY:3|:3766
- 6 - A 13 OR2 0 4 0 1 |DISPLAY:3|:3769
- 7 - A 13 OR2 0 4 0 1 |DISPLAY:3|:3772
- 1 - A 13 OR2 0 4 1 0 |DISPLAY:3|:3775
- 3 - A 24 OR2 0 3 0 1 |DISPLAY:3|:3781
- 5 - A 24 OR2 0 4 0 1 |DISPLAY:3|:3788
- 4 - A 24 OR2 0 4 0 1 |DISPLAY:3|:3789
- 2 - A 24 OR2 0 4 0 1 |DISPLAY:3|:3790
- 2 - A 13 OR2 0 4 1 0 |DISPLAY:3|:3793
- 2 - A 18 OR2 0 4 0 1 |DISPLAY:3|:3799
- 5 - A 11 OR2 0 4 0 1 |DISPLAY:3|:3806
- 8 - A 09 OR2 0 4 0 1 |DISPLAY:3|:3807
- 3 - A 13 OR2 0 4 0 1 |DISPLAY:3|:3808
- 5 - A 13 OR2 0 2 1 0 |DISPLAY:3|:3811
- 5 - A 03 OR2 0 4 0 1 |DISPLAY:3|:3817
- 4 - A 03 OR2 0 4 0 1 |DISPLAY:3|:3820
- 1 - A 16 OR2 0 4 0 1 |DISPLAY:3|:3823
- 2 - A 16 OR2 0 4 0 1 |DISPLAY:3|:3826
- 8 - A 16 OR2 0 4 1 0 |DISPLAY:3|:3829
- 8 - A 23 OR2 0 4 1 1 |DISPLAY:3|:3883
- 4 - C 05 AND2 0 2 0 20 |KSY:5|kand2:U4|:4
- 5 - C 05 DFFE + 0 1 0 2 |KSY:5|kdf:U2|:3
- 1 - C 05 DFFE + 0 1 0 1 |KSY:5|kdf:U2|:5
- 3 - C 05 DFFE + 0 1 0 1 |KSY:5|kdf:U3|:5
- 2 - C 05 OR2 ! 1 1 0 2 |KSY:5|knand2:U0|:6
- 6 - A 01 AND2 0 2 0 1 |KSY:6|kand2:U4|:4
- 3 - A 01 DFFE + 0 1 0 2 |KSY:6|kdf:U2|:3
- 1 - A 01 DFFE + 0 1 0 1 |KSY:6|kdf:U2|:5
- 5 - A 01 DFFE + 0 1 0 1 |KSY:6|kdf:U3|:5
- 2 - A 01 OR2 ! 1 1 0 2 |KSY:6|knand2:U0|:6
- 8 - A 07 OR2 ! 0 2 0 33 |KSY:7|kand2:U4|:4
- 1 - C 14 DFFE + 0 1 0 2 |KSY:7|kdf:U2|:3
- 2 - C 14 DFFE + 0 1 0 1 |KSY:7|kdf:U2|:5
- 7 - A 07 DFFE + 0 1 0 1 |KSY:7|kdf:U3|:5
- 3 - C 14 OR2 ! 1 1 0 2 |KSY:7|knand2:U0|:6
- 1 - A 33 AND2 0 2 0 7 |KSY:8|kand2:U4|:4
- 4 - A 33 DFFE + 0 1 0 2 |KSY:8|kdf:U2|:3
- 2 - A 33 DFFE + 0 1 0 1 |KSY:8|kdf:U2|:5
- 5 - A 33 DFFE + 0 1 0 1 |KSY:8|kdf:U3|:5
- 3 - A 33 OR2 ! 1 1 0 2 |KSY:8|knand2:U0|:6
- 6 - A 07 AND2 0 2 0 1 |KSY:12|kand2:U4|:4
- 4 - A 07 DFFE + 0 1 0 2 |KSY:12|kdf:U2|:3
- 2 - A 07 DFFE + 0 1 0 1 |KSY:12|kdf:U2|:5
- 5 - A 07 DFFE + 0 1 0 1 |KSY:12|kdf:U3|:5
- 3 - A 07 OR2 ! 1 1 0 2 |KSY:12|knand2:U0|:6
- 3 - A 10 OR2 0 4 0 2 |RING:4|LPM_ADD_SUB:204|addcore:adder|pcarry2
- 1 - A 04 OR2 0 3 0 2 |RING:4|LPM_ADD_SUB:204|addcore:adder|pcarry3
- 3 - A 18 OR2 0 4 0 2 |RING:4|LPM_ADD_SUB:204|addcore:adder|:110
- 7 - A 14 OR2 0 2 0 1 |RING:4|LPM_ADD_SUB:204|addcore:adder|:115
- 1 - A 10 OR2 0 4 0 2 |RING:4|LPM_ADD_SUB:204|addcore:adder|:116
- 3 - A 04 OR2 0 3 0 2 |RING:4|LPM_ADD_SUB:204|addcore:adder|:117
- 8 - A 04 OR2 0 4 0 2 |RING:4|LPM_MULT:191|multcore:mult_core|:1378
- 6 - A 14 AND2 0 1 0 4 |RING:4|LPM_MULT:191|multcore:mult_core|:1402
- 8 - A 06 AND2 0 1 0 2 |RING:4|LPM_MULT:191|multcore:mult_core|:1405
- 1 - A 07 DFFE 0 2 0 1 |RING:4|alarmlock (|RING:4|:24)
- 7 - A 25 OR2 s 0 4 0 1 |RING:4|~336~1
- 8 - A 25 AND2 s 0 4 0 1 |RING:4|~336~2
- 5 - A 25 AND2 s 0 4 0 2 |RING:4|~336~3
- 7 - A 04 AND2 0 2 0 1 |RING:4|:336
- 1 - A 14 OR2 0 4 0 1 |RING:4|:1801
- 4 - A 14 OR2 s 0 4 0 1 |RING:4|~2849~1
- 7 - A 01 OR2 0 4 0 1 |RING:4|:2849
- 2 - A 14 OR2 s 0 4 0 1 |RING:4|~2850~1
- 3 - A 14 OR2 s 0 4 0 1 |RING:4|~2850~2
- 5 - A 14 AND2 s 0 4 0 1 |RING:4|~2850~3
- 8 - A 14 AND2 s 0 4 0 1 |RING:4|~2850~4
- 4 - A 04 OR2 s 0 4 0 1 |RING:4|~2850~5
- 5 - A 04 OR2 s 0 3 0 2 |RING:4|~2850~6
- 4 - A 01 OR2 0 4 1 0 |RING:4|:2856
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\eclock.rpt
eclock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 81/144( 56%) 39/ 72( 54%) 16/ 72( 22%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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