📄 eclock.rpt
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Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 85/1728 ( 4%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 5 8 8 1 8 7 8 8 8 7 8 8 8 3 8 8 0 8 8 1 7 8 7 8 8 7 8 8 8 8 8 5 8 8 8 258/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 5 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 5 8 13 1 8 7 8 8 8 7 8 11 8 3 8 8 0 8 8 1 7 8 7 8 8 7 8 8 8 8 8 5 8 8 8 266/0
Device-Specific Information: e:\eda\eclock.rpt
eclock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
177 - - - 16 INPUT ^ 0 0 0 1 alarmlo
176 - - - 15 INPUT ^ 0 0 0 1 BEGAND
80 - - - -- INPUT G ^ 0 0 0 0 cclk
183 - - - -- INPUT G ^ 0 0 0 0 clk
175 - - - 14 INPUT ^ 0 0 0 1 ENTER
174 - - - 14 INPUT ^ 0 0 0 1 KEYUP
173 - - - 13 INPUT ^ 0 0 0 1 RESET
79 - - - -- INPUT G ^ 0 0 0 0 SCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\eclock.rpt
eclock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - E -- OUTPUT 0 1 0 0 ALARM
68 - - - 24 OUTPUT 0 1 0 0 DISSELLECT0
69 - - - 23 OUTPUT 0 1 0 0 DISSELLECT1
70 - - - 22 OUTPUT 0 1 0 0 DISSELLECT2
86 - - - 15 OUTPUT 0 1 0 0 TRANDIS0
87 - - - 14 OUTPUT 0 1 0 0 TRANDIS1
88 - - - 14 OUTPUT 0 1 0 0 TRANDIS2
89 - - - 13 OUTPUT 0 1 0 0 TRANDIS3
90 - - - 12 OUTPUT 0 1 0 0 TRANDIS4
92 - - - 11 OUTPUT 0 1 0 0 TRANDIS5
93 - - - 10 OUTPUT 0 1 0 0 TRANDIS6
94 - - - 09 OUTPUT 0 0 0 0 TRANDIS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\eclock.rpt
eclock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 17 OR2 ! 0 3 0 1 |CLOCK:1|LPM_ADD_SUB:365|addcore:adder|:63
- 2 - A 35 AND2 0 2 0 3 |CLOCK:1|LPM_ADD_SUB:563|addcore:adder|:59
- 3 - A 32 AND2 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:563|addcore:adder|:63
- 3 - A 25 AND2 0 2 0 3 |CLOCK:1|LPM_ADD_SUB:689|addcore:adder|:55
- 4 - A 18 AND2 0 2 0 1 |CLOCK:1|LPM_ADD_SUB:838|addcore:adder|:59
- 3 - A 02 AND2 0 3 0 2 |CLOCK:1|LPM_ADD_SUB:838|addcore:adder|:63
- 2 - A 02 DFFE + 0 4 0 12 |CLOCK:1|seclow3 (|CLOCK:1|:43)
- 1 - A 18 DFFE + 0 4 0 12 |CLOCK:1|seclow2 (|CLOCK:1|:44)
- 5 - A 18 DFFE + 0 4 0 15 |CLOCK:1|seclow1 (|CLOCK:1|:45)
- 8 - A 02 DFFE + 0 2 0 14 |CLOCK:1|seclow0 (|CLOCK:1|:46)
- 1 - A 25 DFFE + 0 4 0 13 |CLOCK:1|sechigh2 (|CLOCK:1|:47)
- 7 - A 19 DFFE + 0 4 0 13 |CLOCK:1|sechigh1 (|CLOCK:1|:48)
- 6 - A 19 DFFE + 0 3 0 12 |CLOCK:1|sechigh0 (|CLOCK:1|:49)
- 4 - A 32 DFFE + 0 4 0 12 |CLOCK:1|minlow3 (|CLOCK:1|:50)
- 5 - A 32 DFFE + 0 4 0 13 |CLOCK:1|minlow2 (|CLOCK:1|:51)
- 1 - A 35 DFFE + 0 4 0 12 |CLOCK:1|minlow1 (|CLOCK:1|:52)
- 6 - A 35 DFFE + 0 4 0 12 |CLOCK:1|minlow0 (|CLOCK:1|:53)
- 3 - A 30 DFFE + 0 4 0 14 |CLOCK:1|minhigh2 (|CLOCK:1|:54)
- 1 - A 30 DFFE + 0 5 0 13 |CLOCK:1|minhigh1 (|CLOCK:1|:55)
- 7 - A 29 DFFE + 0 3 0 13 |CLOCK:1|minhigh0 (|CLOCK:1|:56)
- 3 - A 22 DFFE + 0 5 0 15 |CLOCK:1|hourlow3 (|CLOCK:1|:57)
- 2 - A 20 DFFE + 0 4 0 14 |CLOCK:1|hourlow2 (|CLOCK:1|:58)
- 8 - A 22 DFFE + 0 4 0 17 |CLOCK:1|hourlow1 (|CLOCK:1|:59)
- 4 - A 20 DFFE + 0 3 0 17 |CLOCK:1|hourlow0 (|CLOCK:1|:60)
- 6 - A 28 DFFE + 0 4 0 10 |CLOCK:1|hourhigh1 (|CLOCK:1|:61)
- 3 - A 28 DFFE + 0 4 0 9 |CLOCK:1|hourhigh0 (|CLOCK:1|:62)
- 4 - A 30 AND2 s 0 3 0 2 |CLOCK:1|~219~1
- 8 - A 30 AND2 s 0 4 0 1 |CLOCK:1|~219~2
- 4 - A 22 AND2 s 0 2 0 3 |CLOCK:1|~219~3
- 6 - A 22 AND2 s 0 3 0 1 |CLOCK:1|~219~4
- 2 - A 22 AND2 s 0 3 0 1 |CLOCK:1|~219~5
- 7 - A 28 OR2 s 0 4 0 1 |CLOCK:1|~219~6
- 7 - A 18 OR2 ! 0 4 0 14 |CLOCK:1|:219
- 4 - A 19 OR2 ! 0 3 0 8 |CLOCK:1|:235
- 1 - A 32 OR2 ! 0 4 0 5 |CLOCK:1|:251
- 2 - A 28 OR2 ! 0 4 0 3 |CLOCK:1|:292
- 4 - A 28 OR2 s 0 4 0 2 |CLOCK:1|~507~1
- 8 - A 28 AND2 s 0 3 0 4 |CLOCK:1|~513~1
- 2 - A 30 OR2 s 0 3 0 3 |CLOCK:1|~610~1
- 7 - A 32 OR2 0 4 0 1 |CLOCK:1|:726
- 2 - A 32 OR2 0 4 0 1 |CLOCK:1|:732
- 7 - A 35 OR2 0 4 0 1 |CLOCK:1|:738
- 4 - A 25 OR2 0 4 0 1 |CLOCK:1|:885
- 8 - A 19 OR2 0 4 0 1 |CLOCK:1|:891
- 6 - A 30 OR2 s 0 4 0 1 |CLOCK:1|~926~1
- 5 - A 30 OR2 s 0 4 0 1 |CLOCK:1|~932~1
- 6 - A 32 OR2 s 0 3 0 6 |CLOCK:1|~938~1
- 1 - A 22 OR2 s 0 4 0 1 |CLOCK:1|~944~1
- 8 - A 20 OR2 s 0 4 0 1 |CLOCK:1|~950~1
- 5 - A 22 OR2 s 0 3 0 1 |CLOCK:1|~956~1
- 7 - A 30 OR2 s 0 3 0 6 |CLOCK:1|~962~1
- 5 - A 28 OR2 s 0 4 0 1 |CLOCK:1|~968~1
- 8 - A 34 DFFE 0 2 0 1 |CONTROL:2|adjust~1
- 6 - A 34 DFFE 0 3 0 2 |CONTROL:2|adjust~2
- 7 - A 34 DFFE 0 3 0 4 |CONTROL:2|adjust~3
- 2 - A 34 DFFE 0 3 0 4 |CONTROL:2|adjust~4
- 2 - A 27 DFFE 0 3 0 6 |CONTROL:2|adjust~5
- 8 - A 35 AND2 s 0 2 0 3 |CONTROL:2|adjust~6~2
- 3 - A 27 DFFE 0 3 0 7 |CONTROL:2|adjust~6
- 4 - A 34 OR2 s ! 0 4 0 2 |CONTROL:2|adjust~7~2
- 3 - A 15 AND2 s 0 2 0 2 |CONTROL:2|adjust~7~3
- 3 - A 36 OR2 s 0 4 0 1 |CONTROL:2|adjust~7~4
- 8 - A 15 OR2 s 0 4 0 1 |CONTROL:2|adjust~7~5
- 1 - A 19 OR2 s ! 0 2 0 2 |CONTROL:2|adjust~7~6
- 3 - A 26 AND2 s 0 2 0 1 |CONTROL:2|adjust~7~7
- 5 - A 26 AND2 s 0 2 0 1 |CONTROL:2|adjust~7~8
- 6 - A 26 AND2 s 0 4 0 1 |CONTROL:2|adjust~7~9
- 7 - A 20 OR2 s 0 4 0 1 |CONTROL:2|adjust~7~10
- 7 - A 27 OR2 s 0 4 0 1 |CONTROL:2|adjust~7~11
- 1 - A 34 DFFE 0 4 0 9 |CONTROL:2|adjust~7
- 4 - A 36 AND2 0 2 0 2 |CONTROL:2|LPM_ADD_SUB:789|addcore:adder|:59
- 1 - A 15 OR2 ! 0 2 0 2 |CONTROL:2|LPM_ADD_SUB:1014|addcore:adder|:59
- 8 - A 01 DFFE 0 2 0 20 |CONTROL:2|setmark (|CONTROL:2|:26)
- 4 - A 31 DFFE 0 4 0 14 |CONTROL:2|hourhigh1 (|CONTROL:2|:27)
- 8 - A 31 DFFE 0 4 0 4 |CONTROL:2|hourhigh0 (|CONTROL:2|:28)
- 1 - A 31 DFFE 0 6 0 8 |CONTROL:2|hourlow3 (|CONTROL:2|:29)
- 1 - A 20 DFFE 0 5 0 7 |CONTROL:2|hourlow2 (|CONTROL:2|:30)
- 2 - A 26 DFFE 0 5 0 10 |CONTROL:2|hourlow1 (|CONTROL:2|:31)
- 5 - A 27 DFFE 0 5 0 10 |CONTROL:2|hourlow0 (|CONTROL:2|:32)
- 1 - A 29 DFFE 0 5 0 4 |CONTROL:2|minhigh2 (|CONTROL:2|:33)
- 2 - A 29 DFFE 0 5 0 3 |CONTROL:2|minhigh1 (|CONTROL:2|:34)
- 4 - A 29 DFFE 0 5 0 3 |CONTROL:2|minhigh0 (|CONTROL:2|:35)
- 1 - A 36 DFFE 0 5 0 6 |CONTROL:2|minlow3 (|CONTROL:2|:36)
- 2 - A 36 DFFE 0 5 0 5 |CONTROL:2|minlow2 (|CONTROL:2|:37)
- 5 - A 35 DFFE 0 5 0 6 |CONTROL:2|minlow1 (|CONTROL:2|:38)
- 3 - A 35 DFFE 0 5 0 8 |CONTROL:2|minlow0 (|CONTROL:2|:39)
- 8 - A 29 DFFE 0 5 0 5 |CONTROL:2|sechigh2 (|CONTROL:2|:40)
- 5 - A 19 DFFE 0 5 0 3 |CONTROL:2|sechigh1 (|CONTROL:2|:41)
- 2 - A 19 DFFE 0 5 0 3 |CONTROL:2|sechigh0 (|CONTROL:2|:42)
- 1 - A 02 DFFE 0 5 0 6 |CONTROL:2|seclow3 (|CONTROL:2|:43)
- 2 - A 15 DFFE 0 5 0 5 |CONTROL:2|seclow2 (|CONTROL:2|:44)
- 6 - A 15 DFFE 0 5 0 6 |CONTROL:2|seclow1 (|CONTROL:2|:45)
- 4 - A 15 DFFE 0 5 0 8 |CONTROL:2|seclow0 (|CONTROL:2|:46)
- 1 - A 27 OR2 0 4 0 5 |CONTROL:2|:345
- 6 - A 27 OR2 s ! 0 2 0 1 |CONTROL:2|~347~1
- 8 - A 36 OR2 0 4 0 4 |CONTROL:2|:746
- 4 - A 02 OR2 0 4 0 5 |CONTROL:2|:971
- 3 - A 34 OR2 s ! 0 3 0 5 |CONTROL:2|~1108~1
- 6 - A 02 OR2 s 0 4 0 1 |CONTROL:2|~1108~2
- 7 - A 02 OR2 s 0 4 0 1 |CONTROL:2|~1108~3
- 5 - A 15 OR2 s 0 4 0 1 |CONTROL:2|~1129~1
- 7 - A 15 OR2 s 0 4 0 1 |CONTROL:2|~1150~1
- 3 - A 19 OR2 s 0 4 0 1 |CONTROL:2|~1180~1
- 6 - A 29 OR2 s 0 4 0 1 |CONTROL:2|~1186~1
- 5 - A 34 AND2 s 0 4 0 5 |CONTROL:2|~1255~1
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