📄 eclock.rpt
字号:
|ksy:6|knand2:U0|
|ksy:6|knand2:U1|
|ksy:6|kdf:U2|
|ksy:6|kdf:U3|
|ksy:6|kand2:U4|
|ksy:8|
|ksy:8|knand2:U0|
|ksy:8|knand2:U1|
|ksy:8|kdf:U2|
|ksy:8|kdf:U3|
|ksy:8|kand2:U4|
Device-Specific Information: e:\eda\eclock.rpt
eclock
***** Logic for device 'eclock' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E a E E E E E E E E E E E E E E
S S S S S S S V S S S S S S S S S S S S S V S S l B S S S S S S S S S S S S S S
E E E E E E E C E E E E E E V E E E E E E E C E E V a E E K R E E E E E E V E E E E E E E E
R R R R R R R C R R R R R R C R R R R R R R C R R C r G N E E R R R R R R C R R R R R R R R
V V V V V V V I V V V V V V C V V V V V G V V I G c G G V V C m A T Y S V G V V V V V C V V V V V V V V
E E E E E E E N E E E E E E I E E E E E N E E N N l N N E E I l N E U E E N E E E E E I E E E E E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D k D D D D O o D R P T D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
ALARM | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R D D D R V R R R G V G S c G G R V R T T T T T V T T T R R R V R R R R R R
E E E E E E N E E E E E E C E I I I E C E E E N C N C c N N E C E R R R R R C R R R E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S S D C D L l D D S C S A A A A A C A A A S S S C S S S S S S
E E E E E E E E E E E E I E S S S E I E E E I K k E I E N N N N N I N N N E E E I E E E E E E
R R R R R R R R R R R R O R E E E R N R R R N R O R D D D D D N D D D R R R O R R R R R R
V V V V V V V V V V V V V L L L V T V V V T V V I I I I I T I I I V V V V V V V V V
E E E E E E E E E E E E E L L L E E E E E E S S S S S S S S E E E E E E E E E
D D D D D D D D D D D D D E E E D D D D D D 0 1 2 3 4 5 6 7 D D D D D D D D D
C C C
T T T
0 1 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\eda\eclock.rpt
eclock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 7/22( 31%)
A2 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 2/2 10/22( 45%)
A3 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
A4 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
A5 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
A7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 2/22( 9%)
A8 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
A9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
A10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
A12 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
A13 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
A14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
A15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
A16 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
A17 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 12/22( 54%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 8/22( 36%)
A20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 14/22( 63%)
A21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A22 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
A23 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 2/22( 9%)
A24 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
A25 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 16/22( 72%)
A26 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
A27 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 10/22( 45%)
A28 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
A29 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 9/22( 40%)
A30 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
A31 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
A32 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
A33 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A34 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
A35 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 2/2 10/22( 45%)
A36 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
C5 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C14 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 17/141 ( 12%)
Total logic cells used: 266/1728 ( 15%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.31/4 ( 82%)
Total fan-in: 882/6912 ( 12%)
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 266
Total flipflops required: 67
Total packed registers required: 0
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