eclock.rpt

maxplus2变得电子钟程序/// /// /////

Project Information                                          e:\eda\eclock.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/07/2005 20:57:17

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

eclock    EP1K30QC208-3    8      12     0    0         0  %    266      15 %

User Pins:                 8      12     0  



Project Information                                          e:\eda\eclock.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

eclock@38                         ALARM
eclock@177                        alarmlo
eclock@176                        BEGAND
eclock@80                         cclk
eclock@183                        clk
eclock@68                         DISSELLECT0
eclock@69                         DISSELLECT1
eclock@70                         DISSELLECT2
eclock@175                        ENTER
eclock@174                        KEYUP
eclock@173                        RESET
eclock@79                         SCLK
eclock@86                         TRANDIS0
eclock@87                         TRANDIS1
eclock@88                         TRANDIS2
eclock@89                         TRANDIS3
eclock@90                         TRANDIS4
eclock@92                         TRANDIS5
eclock@93                         TRANDIS6
eclock@94                         TRANDIS7


Project Information                                          e:\eda\eclock.rpt

** STATE MACHINE ASSIGNMENTS **


|CONTROL:2|adjust: MACHINE
        OF BITS (
           |CONTROL:2|adjust~7,
           |CONTROL:2|adjust~6,
           |CONTROL:2|adjust~5,
           |CONTROL:2|adjust~4,
           |CONTROL:2|adjust~3,
           |CONTROL:2|adjust~2,
           |CONTROL:2|adjust~1
        )
        WITH STATES (
                           sethh = B"1000001", 
                           sethl = B"0100001", 
                           setmh = B"0010001", 
                           setml = B"0001001", 
                           setsh = B"0000101", 
                           setsl = B"0000011", 
                             ini = B"0000000"
);



Project Information                                          e:\eda\eclock.rpt

** FILE HIERARCHY **



|clock:1|
|clock:1|lpm_add_sub:325|
|clock:1|lpm_add_sub:325|addcore:adder|
|clock:1|lpm_add_sub:325|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:325|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:325|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:365|
|clock:1|lpm_add_sub:365|addcore:adder|
|clock:1|lpm_add_sub:365|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:365|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:365|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:463|
|clock:1|lpm_add_sub:463|addcore:adder|
|clock:1|lpm_add_sub:463|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:463|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:463|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:563|
|clock:1|lpm_add_sub:563|addcore:adder|
|clock:1|lpm_add_sub:563|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:563|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:563|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:689|
|clock:1|lpm_add_sub:689|addcore:adder|
|clock:1|lpm_add_sub:689|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:689|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:689|altshift:oflow_ext_latency_ffs|
|clock:1|lpm_add_sub:838|
|clock:1|lpm_add_sub:838|addcore:adder|
|clock:1|lpm_add_sub:838|altshift:result_ext_latency_ffs|
|clock:1|lpm_add_sub:838|altshift:carry_ext_latency_ffs|
|clock:1|lpm_add_sub:838|altshift:oflow_ext_latency_ffs|
|control:2|
|control:2|lpm_add_sub:271|
|control:2|lpm_add_sub:271|addcore:adder|
|control:2|lpm_add_sub:271|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:271|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:271|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:388|
|control:2|lpm_add_sub:388|addcore:adder|
|control:2|lpm_add_sub:388|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:388|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:388|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:515|
|control:2|lpm_add_sub:515|addcore:adder|
|control:2|lpm_add_sub:515|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:515|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:515|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:677|
|control:2|lpm_add_sub:677|addcore:adder|
|control:2|lpm_add_sub:677|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:677|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:677|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:789|
|control:2|lpm_add_sub:789|addcore:adder|
|control:2|lpm_add_sub:789|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:789|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:789|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:902|
|control:2|lpm_add_sub:902|addcore:adder|
|control:2|lpm_add_sub:902|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:902|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:902|altshift:oflow_ext_latency_ffs|
|control:2|lpm_add_sub:1014|
|control:2|lpm_add_sub:1014|addcore:adder|
|control:2|lpm_add_sub:1014|altshift:result_ext_latency_ffs|
|control:2|lpm_add_sub:1014|altshift:carry_ext_latency_ffs|
|control:2|lpm_add_sub:1014|altshift:oflow_ext_latency_ffs|
|display:3|
|ring:4|
|ring:4|lpm_mult:191|
|ring:4|lpm_mult:191|multcore:mult_core|
|ring:4|lpm_mult:191|multcore:mult_core|csa_add:padder|
|ring:4|lpm_mult:191|altshift:external_latency_ffs|
|ring:4|lpm_add_sub:204|
|ring:4|lpm_add_sub:204|addcore:adder|
|ring:4|lpm_add_sub:204|altshift:result_ext_latency_ffs|
|ring:4|lpm_add_sub:204|altshift:carry_ext_latency_ffs|
|ring:4|lpm_add_sub:204|altshift:oflow_ext_latency_ffs|
|ksy:5|
|ksy:5|knand2:U0|
|ksy:5|knand2:U1|
|ksy:5|kdf:U2|
|ksy:5|kdf:U3|
|ksy:5|kand2:U4|
|ksy:12|
|ksy:12|knand2:U0|
|ksy:12|knand2:U1|
|ksy:12|kdf:U2|
|ksy:12|kdf:U3|
|ksy:12|kand2:U4|
|ksy:7|
|ksy:7|knand2:U0|
|ksy:7|knand2:U1|
|ksy:7|kdf:U2|
|ksy:7|kdf:U3|
|ksy:7|kand2:U4|
|ksy:6|