📄 csl_vphal.h
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/******************************************************************************\* Copyright (C) 2002-2004 Texas Instruments Incorporated.* All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_vphal.h* DATE CREATED.. 12/06/2001 * updated for version 1.3.............01/10/2002* LAST MODIFIED. 02/28/2002**------------------------------------------------------------------------------* REGISTERS********************************************************************************* Memory Mapping Register -- Global** VPPID0 - Video Port 0 Peripheral Identification Register* VPPID1 - Video Port 1 Peripheral Identification Register* VPPID2 - Video Port 2 Peripheral Identification Register* PCR0 - Video Port 0 Peripheral Control * PCR1 - Video Port 1 Peripheral Control* PCR2 - Video Port 2 Peripheral Control* PFUNC0 - Video Port 0 Pin Function* PFUNC1 - Video Port 1 Pin Function* PFUNC2 - Video Port 2 Pin Function* PDIR0 - Video Port 0 Pin Direction* PDIR1 - Video Port 1 Pin Direction* PDIR2 - Video Port 2 Pin Direction* PDIN0 - Video Port 0 Pin Data In* PDIN1 - Video Port 1 Pin Data In* PDIN2 - Video Port 2 Pin Data In* PDOUT0 - Video Port 0 Pin Data Out* PDOUT1 - Video Port 1 Pin Data Out* PDOUT2 - Video Port 2 Pin Data Out* PDSET0 - Video Port 0 Pin Data Set* PDSET1 - Video Port 1 Pin Data Set* PDSET2 - Video Port 2 Pin Data Set* PDCLR0 - Video Port 0 Pin Data Clear* PDCLR1 - Video Port 1 Pin Data Clear* PDCLR2 - Video Port 2 Pin Data Clear* PIEN0 - Video Port 0 Pin Interrupt Enable* PIEN1 - Video Port 1 Pin Interrupt Enable* PIEN2 - Video Port 2 Pin Interrupt Enable* PIPOL0 - Video Port 0 Pin Interrupt Polarity* PIPOL1 - Video Port 1 Pin Interrupt Polarity* PIPOL2 - Video Port 2 Pin Interrupt Polarity* PISTAT0 - Video Port 0 Pin Interrupt Status* PISTAT1 - Video Port 1 Pin Interrupt Status* PISTAT2 - Video Port 2 Pin Interrupt Status* PICLR0 - Video Port 0 Pin Interrupt Clear* PICLR1 - Video Port 1 Pin Interrupt Clear* PICLR2 - Video Port 2 Pin Interrupt Clear* VPCTL0 - Video Port 0 Control Register* VPCTL1 - Video Port 1 Control Register* VPCTL2 - Video Port 2 Control Register* VPSTAT0 - Video Port 0 Status Register * VPSTAT1 - Video Port 1 Status Register * VPSTAT2 - Video Port 2 Status Register * VPIE0 - Video Port 0 Interrupt Enable Register* VPIE1 - Video Port 1 Interrupt Enable Register* VPIE2 - Video Port 2 Interrupt Enable Register* VPIS0 - Video Port 0 Interrupt Status Register* VPIS1 - Video Port 1 Interrupt Status Register* VPIS2 - Video Port 2 Interrupt Status Register********************************************************************************* Memory Mapping Register -- Capture** VCASTAT0 - Video Port 0 Video Capture A Status* VCASTAT1 - Video Port 1 Video Capture A Status* VCASTAT2 - Video Port 2 Video Capture A Status* VCACTL0 - Video Port 0 Video Capture A Control* VCACTL1 - Video Port 1 Video Capture A Control* VCACTL2 - Video Port 2 Video Capture A Control* VCASTRT10 - Video Port 0 Video Capture A Field1 Start* VCASTRT11 - Video Port 1 Video Capture A Field1 Start* VCASTRT12 - Video Port 2 Video Capture A Field1 Start* VCASTOP10 - Video Port 0 Video Capture A Field1 Stop* VCASTOP11 - Video Port 1 Video Capture A Field1 Stop* VCASTOP12 - Video Port 2 Video Capture A Field1 Stop* VCASTRT20 - Video Port 0 Video Capture A Field2 Start* VCASTRT21 - Video Port 1 Video Capture A Field2 Start* VCASTRT22 - Video Port 2 Video Capture A Field2 Start* VCASTOP20 - Video Port 0 Video Capture A Field2 Stop* VCASTOP21 - Video Port 1 Video Capture A Field2 Stop* VCASTOP22 - Video Port 2 Video Capture A Field2 Stop* VCAVINT0 - Video Port 0 Video Capture A Vertical Interrupt* VCAVINT1 - Video Port 1 Video Capture A Vertical Interrupt* VCAVINT2 - Video Port 2 Video Capture A Vertical Interrupt* VCATHRLD0 - Video Port 0 Video Capture A Threshold* VCATHRLD1 - Video Port 1 Video Capture A Threshold* VCATHRLD2 - Video Port 2 Video Capture A Threshold* VCAEVTCT0 - Video Port 0 Video Capture A Event Count* VCAEVTCT1 - Video Port 1 Video Capture A Event Count* VCAEVTCT2 - Video Port 2 Video Capture A Event Count** VCBSTAT0 - Video Port 0 Video Capture B Status* VCBSTAT1 - Video Port 1 Video Capture B Status* VCBSTAT2 - Video Port 2 Video Capture B Status* VCBCTL0 - Video Port 0 Video Capture B Control* VCBCTL1 - Video Port 1 Video Capture B Control* VCBCTL2 - Video Port 2 Video Capture B Control* VCBSTRT10 - Video Port 0 Video Capture B Field1 Start* VCBSTRT11 - Video Port 1 Video Capture B Field1 Start* VCBSTRT12 - Video Port 2 Video Capture B Field1 Start* VCBSTOP10 - Video Port 0 Video Capture B Field1Stop* VCBSTOP11 - Video Port 1 Video Capture B Field1Stop* VCBSTOP12 - Video Port 2 Video Capture B Field1Stop* VCBSTRT20 - Video Port 0 Video Capture B Field2 Start* VCBSTRT21 - Video Port 1 Video Capture B Field2 Start* VCBSTRT22 - Video Port 2 Video Capture B Field2 Start* VCBSTOP20 - Video Port 0 Video Capture B Field2Stop* VCBSTOP21 - Video Port 1 Video Capture B Field2Stop* VCBSTOP22 - Video Port 2 Video Capture B Field2Stop* VCBVINT0 - Video Port 0 Video Capture B Vertical Interrupt* VCBVINT1 - Video Port 1 Video Capture B Vertical Interrupt* VCBVINT2 - Video Port 2 Video Capture B Vertical Interrupt* VCBTHRLD0 - Video Port 0 Video Capture B Threshold* VCBTHRLD1 - Video Port 1 Video Capture B Threshold* VCBTHRLD2 - Video Port 2 Video Capture B Threshold* VCBEVTCT0 - Video Port 0 Video Capture B Event Count* VCBEVTCT1 - Video Port 1 Video Capture B Event Count* VCBEVTCT2 - Video Port 2 Video Capture B Event Count** TSICTL0 - Video Port 0 Transport Stream Interface Capture Control* TSICTL1 - Video Port 1 Transport Stream Interface Capture Control* TSICTL2 - Video Port 2 Transport Stream Interface Capture Control* TSICLKINITL0 - Video Port 0 Transport Stream Interface Clock Initialization LSB* TSICLKINITL1 - Video Port 1 Transport Stream Interface Clock Initialization LSB* TSICLKINITL2 - Video Port 2 Transport Stream Interface Clock Initialization LSB* TSICLKINITM0 - Video Port 0 Transport Stream Interface Clock Initialization MSB* TSICLKINITM1 - Video Port 1 Transport Stream Interface Clock Initialization MSB* TSICLKINITM2 - Video Port 2 Transport Stream Interface Clock Initialization MSB* TSISTCLKL0 - Video Port 0 Transport Stream Interface System Time Clock LSB* TSISTCLKL1 - Video Port 1 Transport Stream Interface System Time Clock LSB* TSISTCLKL2 - Video Port 2 Transport Stream Interface System Time Clock LSB* TSISTCLKM0 - Video Port 0 Transport Stream Interface System Time Clock MSB* TSISTCLKM1 - Video Port 1 Transport Stream Interface System Time Clock MSB* TSISTCLKM2 - Video Port 2 Transport Stream Interface System Time Clock MSB* TSISTCMPL0 - Video Port 0 Transport Stream Interface STC Compare LSB* TSISTCMPL1 - Video Port 1 Transport Stream Interface STC Compare LSB* TSISTCMPL2 - Video Port 2 Transport Stream Interface STC Compare LSB* TSISTCMPM0 - Video Port 0 Transport Stream Interface STC Compare MSB* TSISTCMPM1 - Video Port 1 Transport Stream Interface STC Compare MSB* TSISTCMPM2 - Video Port 2 Transport Stream Interface STC Compare MSB* TSISTMSKL0 - Video Port 0 Transport Stream Interface STC Compare Mask LSB* TSISTMSKL1 - Video Port 1 Transport Stream Interface STC Compare Mask LSB* TSISTMSKL2 - Video Port 2 Transport Stream Interface STC Compare Mask LSB* TSISTMSKM0 - Video Port 0 Transport Stream Interface STC Compare Mask MSB* TSISTMSKM1 - Video Port 1 Transport Stream Interface STC Compare Mask MSB* TSISTMSKM2 - Video Port 2 Transport Stream Interface STC Compare Mask MSB* TSITICKS0 - Video Port 0 Transport Stream Interface STC Ticks Interrupt* TSITICKS1 - Video Port 1 Transport Stream Interface STC Ticks Interrupt* TSITICKS2 - Video Port 2 Transport Stream Interface STC Ticks Interrupt********************************************************************************** Memory Mapping Register -- Display** VDSTAT0 - Video Port 0 Video Display Status* VDSTAT1 - Video Port 1 Video Display Status* VDSTAT2 - Video Port 2 Video Display Status* VDCTL0 - Video Port 0 Video Display Control* VDCTL1 - Video Port 1 Video Display Control* VDCTL2 - Video Port 2 Video Display Control* VDFRMSZ0 - Video Port 0 Video Display Frame Size* VDFRMSZ1 - Video Port 1 Video Display Frame Size* VDFRMSZ2 - Video Port 2 Video Display Frame Size* VDHBLNK0 - Video Port 0 Video Display Horizontal Blanking* VDHBLNK1 - Video Port 1 Video Display Horizontal Blanking* VDHBLNK2 - Video Port 2 Video Display Horizontal Blanking* VDVBLKS10 - Video Port 0 Video Display Vertical Blanking Start - Field 1* VDVBLKS11 - Video Port 1 Video Display Vertical Blanking Start - Field 1* VDVBLKS12 - Video Port 2 Video Display Vertical Blanking Start - Field 1* VDVBLKE10 - Video Port 0 Video Display Vertical Blanking End - Field 1* VDVBLKE11 - Video Port 1 Video Display Vertical Blanking End - Field 1* VDVBLKE12 - Video Port 2 Video Display Vertical Blanking End - Field 1* VDVBLKS20 - Video Port 0 Video Display Vertical Blanking Start - Field 2* VDVBLKS21 - Video Port 1 Video Display Vertical Blanking Start - Field 2* VDVBLKS22 - Video Port 2 Video Display Vertical Blanking Start - Field 2* VDVBLKE20 - Video Port 0 Video Display Vertical Blanking End - Field 2* VDVBLKE21 - Video Port 1 Video Display Vertical Blanking End - Field 2* VDVBLKE22 - Video Port 2 Video Display Vertical Blanking End - Field 2* VDIMGOFF10 - Video Port 0 Video Display Image Offset - Field 1* VDIMGOFF11 - Video Port 1 Video Display Image Offset - Field 1* VDIMGOFF12 - Video Port 2 Video Display Image Offset - Field 1* VDIMGSZ10 - Video Port 0 Video Display Image Size - Field 1* VDIMGSZ11 - Video Port 1 Video Display Image Size - Field 1* VDIMGSZ12 - Video Port 2 Video Display Image Size - Field 1* VDIMGOFF20 - Video Port 0 Video Display Image Offset - Field 2* VDIMGOFF21 - Video Port 1 Video Display Image Offset - Field 2* VDIMGOFF22 - Video Port 2 Video Display Image Offset - Field 2* VDIMGSZ20 - Video Port 0 Video Display Image Size - Field 2* VDIMGSZ21 - Video Port 1 Video Display Image Size - Field 2* VDIMGSZ22 - Video Port 2 Video Display Image Size - Field 2* VDFLDT10 - Video Port 0 Video Display Field1 Timing* VDFLDT11 - Video Port 1 Video Display Field1 Timing* VDFLDT12 - Video Port 2 Video Display Field1 Timing* VDFLDT20 - Video Port 0 Video Display Field2 Timing* VDFLDT21 - Video Port 1 Video Display Field2 Timing* VDFLDT22 - Video Port 2 Video Display Field2 Timing* VDTHRLD0 - Video Port 0 Video Display Threshold* VDTHRLD1 - Video Port 1 Video Display Threshold* VDTHRLD2 - Video Port 2 Video Display Threshold* VDHSYNC0 - Video Port 0 Video Display Horizontal Sync* VDHSYNC1 - Video Port 1 Video Display Horizontal Sync* VDHSYNC2 - Video Port 2 Video Display Horizontal Sync* VDVSYNS10 - Video Port 0 Video Display Vertical Synchronization Start - Field 1* VDVSYNS11 - Video Port 1 Video Display Vertical Synchronization Start - Field 1* VDVSYNS12 - Video Port 2 Video Display Vertical Synchronization Start - Field 1* VDVSYNE10 - Video Port 0 Video Display Vertical Synchronization End - Field 1* VDVSYNE11 - Video Port 1 Video Display Vertical Synchronization End - Field 1* VDVSYNE12 - Video Port 2 Video Display Vertical Synchronization End - Field 1* VDVSYNS20 - Video Port 0 Video Display Vertical Synchronization Start - Field 2* VDVSYNS21 - Video Port 1 Video Display Vertical Synchronization Start - Field 2* VDVSYNS22 - Video Port 2 Video Display Vertical Synchronization Start - Field 2* VDVSYNE20 - Video Port 0 Video Display Vertical Synchronization End - Field 2* VDVSYNE21 - Video Port 1 Video Display Vertical Synchronization End - Field 2* VDVSYNE22 - Video Port 2 Video Display Vertical Synchronization End - Field 2* VDRELOAD0 - Video Port 0 Video Display Counter Reload* VDRELOAD1 - Video Port 1 Video Display Counter Reload* VDRELOAD2 - Video Port 2 Video Display Counter Reload* VDDISPEVT0 - Video Port 0 Video Display Display Event Register* VDDISPEVT1 - Video Port 1 Video Display Display Event Register* VDDISPEVT2 - Video Port 2 Video Display Display Event Register* VDCLIP0 - Video Port 0 Video Display Clipping Register* VDCLIP1 - Video Port 1 Video Display Clipping Register* VDCLIP2 - Video Port 2 Video Display Clipping Register* VDDEFVAL0 - Video Port 0 Video Display Default Display Value* VDDEFVAL1 - Video Port 1 Video Display Default Display Value* VDDEFVAL2 - Video Port 2 Video Display Default Display Value* VDVINT0 - Video Port 0 Video Display Vertical Interrupt* VDVINT1 - Video Port 1 Video Display Vertical Interrupt* VDVINT2 - Video Port 2 Video Display Vertical Interrupt* VDFBIT0 - Video Port 0 Video Display Field Bit Register* VDFBIT1 - Video Port 1 Video Display Field Bit Register* VDFBIT2 - Video Port 2 Video Display Field Bit Register* VDVBIT10 - Video Port 0 Video Display Vertical Blank Bit-Field 1 Register* VDVBIT11 - Video Port 1 Video Display Vertical Blank Bit-Field 1 Register* VDVBIT12 - Video Port 2 Video Display Vertical Blank Bit-Field 1 Register* VDVBIT20 - Video Port 0 Video Display Vertical Blank Bit-Field 2 Register* VDVBIT21 - Video Port 1 Video Display Vertical Blank Bit-Field 2 Register* VDVBIT22 - Video Port 2 Video Display Vertical Blank Bit-Field 2 Register********************************************************************************** FIFO Mapping** YSRCA0 - Video Port 0 Y FIFO Source Register A* YSRCA1 - Video Port 1 Y FIFO Source Register A* YSRCA2 - Video Port 2 Y FIFO Source Register A* CBSRCA0 - Video Port 0 Cb FIFO Source Register A* CBSRCA1 - Video Port 1 Cb FIFO Source Register A* CBSRCA2 - Video Port 2 Cb FIFO Source Register A* CRSRCA0 - Video Port 0 Cr FIFO Source Register A* CRSRCA1 - Video Port 1 Cr FIFO Source Register A* CRSRCA2 - Video Port 2 Cr FIFO Source Register A* YSRCB0 - Video Port 0 Y FIFO Source Register B* YSRCB1 - Video Port 1 Y FIFO Source Register B* YSRCB2 - Video Port 2 Y FIFO Source Register B* CBSRCB0 - Video Port 0 Cb FIFO Source Register B* CBSRCB1 - Video Port 1 Cb FIFO Source Register B* CBSRCB2 - Video Port 2 Cb FIFO Source Register B* CRSRCB0 - Video Port 0 Cr FIFO Source Register B* CRSRCB1 - Video Port 1 Cr FIFO Source Register B* CRSRCB2 - Video Port 2 Cr FIFO Source Register B* YDSTA0 - Video Port 0 Y FIFO Destination Register A* YDSTA1 - Video Port 1 Y FIFO Destination Register A* YDSTA2 - Video Port 2 Y FIFO Destination Register A* CBDST0 - Video Port 0 Cb FIFO Destination Register * CBDST1 - Video Port 1 Cb FIFO Destination Register * CBDST2 - Video Port 2 Cb FIFO Destination Register * CRDST0 - Video Port 0 Cr FIFO Destination Register* CRDST1 - Video Port 1 Cr FIFO Destination Register* CRDST2 - Video Port 2 Cr FIFO Destination Register* YDSTB0 - Video Port 0 Y FIFO Destination Register B* YDSTB1 - Video Port 1 Y FIFO Destination Register B* YDSTB2 - Video Port 2 Y FIFO Destination Register B*\******************************************************************************/#ifndef _CSL_VPHAL_H_#define _CSL_VPHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (VP_SUPPORT)/******************************************************************************\* MISC section\******************************************************************************/ #define _VP_PORT_CNT 3 #define _VP_BASE_PORT0 0x01C40000u #define _VP_BASE_PORT1 0x01C44000u #define _VP_BASE_PORT2 0x01C48000u/* Capture Channel A base address */ #define _VP_BASE_CHAPORT0 _VP_BASE_PORT0 + 0x00000100u #define _VP_BASE_CHAPORT1 _VP_BASE_PORT1 + 0x00000100u #define _VP_BASE_CHAPORT2 _VP_BASE_PORT2 + 0x00000100u/* Capture Channel B base address */ #define _VP_BASE_CHBPORT0 _VP_BASE_PORT0 + 0x00000140u #define _VP_BASE_CHBPORT1 _VP_BASE_PORT1 + 0x00000140u #define _VP_BASE_CHBPORT2 _VP_BASE_PORT2 + 0x00000140u #define _VP_AFBASE_PORT0 0x74000000u #define _VP_BFBASE_PORT0 0x76000000u #define _VP_AFBASE_PORT1 0x78000000u #define _VP_BFBASE_PORT1 0x7A000000u #define _VP_AFBASE_PORT2 0x7C000000u #define _VP_BFBASE_PORT2 0x7E000000u⌨️ 快捷键说明
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