rominit.s

VxWorks下 Mv2100的BSP源码

kahluaFpuDisabled:
	lwz	r8,0(r6)
	subf	r18,r13,r14		/* calculate number of bytes */
	rlwinm	r18,r18,30,2,31		/* calculate number of words */
	addi	r17,r13,-4		/* starting address munged */
	mtspr	9,r18			/* load number of doubles/words */
	b	kahluaScrubLoopNoFpu	/* branch to loop */

        /* Loop through the entire DRAM array, initialize memory */

kahluaScrubLoopFpu:
	stfdu	0,8(r17)
	bc	16,0,kahluaScrubLoopFpu	/* branch till counter == 0 */
	sync				/* synchronize the data stream */
	b	kahluaScrubExit

kahluaScrubLoopNoFpu:
        /* 
         * Flicker fail LED while scrubbing (demonstrates how slow 
         * (~5 secs) this is. 
         */

#ifdef DEBUG_STARTUP 
        addis	r3,r0,HIADJ(MV2100_SYS_STAT_REG2)	
        ori	r3,r3,LO(MV2100_SYS_STAT_REG2)
	addis	r4,r0,HIADJ(MV2100_BD_FAIL)
	ori	r4,r4,LO(MV2100_BD_FAIL)
	andc	r5,r5,r4		/* and in complement of BD_FAIL */
	stwbrx	r5,r0,r3		/* write new STAT */
	sync				/* ensure memory access is complete */
#endif /* DEBUG_STARTUP */

	stw	r8,4(r17)

#ifdef DEBUG_STARTUP 
        addis	r3,r0,HIADJ(MV2100_SYS_STAT_REG2)	
        ori	r3,r3,LO(MV2100_SYS_STAT_REG2)
        addis	r4,r0,HIADJ(MV2100_BD_FAIL)
        ori	r4,r4,LO(MV2100_BD_FAIL)
	stwbrx	r4,r0,r3		/* write new STAT */
	sync				/* ensure memory access is complete */
#endif /* DEBUG_STARTUP */
	bc	16,0,kahluaScrubLoopNoFpu /* branch till counter == 0 */
	sync				/* synchronize the data stream */

        /* exit */

kahluaScrubExit:
	addi	r3,r0,0			/* initialize error indicator, none */
	mtspr	8,r16			/* restore return instruction pointer */
	bclr    0x14,0x0		/* return to caller */


/******************************************************************************
*
* kahluaRegMod - PCI configuration register modification.
*
* This function provides modification control for Kahlua's
* configuration registers.  It performs the necessary byte
* swapping.
*
* call:
*     kahluaRegMod(regOffset, regSize, mask, data)
*
*     regOffset	= (r3) address of device register to be modified
*     regSize		= (r4) register size
*         1, byte (8 bit) register
*         2, half word (16 bit/2 byte) register
*         4, word (32 bit/4 byte) register
*     mask		= (r5) mask for current register value
*     data		= (r6) data to be inserted into register
*     spr8		= return program counter
*
* registers used (and not saved):
*	r3, r4, r5, r6, r7, r8, r9, r20
*
* RETURNS:
*    (r3) data read from register if read operation (otherwise return 0)
*/

	.text
	.align	2
	FUNC_EXPORT(kahluaRegMod)
kahluaRegMod:
	sync				/* ensure instructions are complete */
	eieio				/* ensures memory access is complete */
	xor	r0,r0,r0		/* clear r0 */

        /* load register addresses to device-register, PCI_CAR, and PCI_CDR */

	addis	r7,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r7,r7,LO(CNFG_PCI_HOST_BRDG)
	add	r7,r7,r3		/* add register offset */
	addis	r8,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r8,r8,LO(PCI_MSTR_PRIMARY_CAR)
	addis	r9,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r9,r9,LO(PCI_MSTR_PRIMARY_CDR)

        /* adjust the addresses to CDR and device-register */

	andi.	r12,r3,0x3		/* mask register offset */
	add	r9,r9,r12		/* adjust it */
	addi	r12,r0,0x3		/* load mask (lower 2-bits) */
	andc	r7,r7,r12		/* mask of lower 2-bits */

        /* write register value to CAR */

	stwbrx	r7,r0,r8		/* write register value to CAR */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */

        /* determine the size of the data operation */

	cmpli	0,0,r4,0x04		/* is this a word i/o operation? */
	bc	0x0c,0x02,andor32	/* branch to word i/o code */
	cmpli	0,0,r4,0x02		/* is this a half-word i/o operation? */
	bc	0x0c,0x02,andor16	/* branch to half-word i/o code */
	cmpli	0,0,r4,0x01		/* is this a byte i/o operation? */
	bc	0x0c,0x02,andor8	/* branch to byte i/o code */
	bclr	0x14,0x0		/* return to caller */

        /* word size data operations */

andor32:				/* READ/MODIFY(AND/OR)/WRITE */
	lwbrx	r7,r0,r9		/* load(read) device data into r7 */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stwbrx	r7,r0,r9		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr    0x14,0x0		/* return to caller */

        /* half-word size data operations */

andor16:				/* READ/MODIFY(AND/OR)/WRITE */
	lhbrx	r7,r0,r9		/* load(read) device data into r7 */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	sthbrx	r7,r0,r9		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr    0x14,0x0		/* return to caller */

        /* byte data size operations */

andor8:					/* READ/MODIFY(AND/OR)/WRITE */
	lbz	r7,0(r9)		/* load(read) device data into r7 */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stb	r7,0(r9)		/* store(write) r7 to device reg */
	eieio				/* ensure memory access is complete */
	sync				/* ensure memory access is complete */
	bclr    0x14,0x0		/* return to caller */


/******************************************************************************
*
* kahluaDefInit - configure memory controller with default memory settings.
*
* This function initializes the Kahlua memory controller
* to bank 0, 32Mg and assumes a 83.3MHz clock.
*
* registers used (and not saved):
*	r3, r4, r5, r6, r7, r8, r9, r20
*
* RETURNS:
*     none
*/

	.text
	.align	3
	FUNC_BEGIN(kahluaDefInit)
	addis	r0,r0,0			/* insure r0 is zero */
	ori	r0,r0,0			/* insure r0 is zero */
	or	r22,r0,r0		/* preset to no memory available */
	mfspr	r20,8			/* save return instruction pointer */

	bl	kahluaInitTableBasicPtr	/* branch around tables */
/*
 *	register data table (initialization values)
 *
 *	this table places the Kahlua into a known state, other tables
 *	exist for specific memory configurations
 */
kahluaInitTableBasic:
/*
 *              reg size  data        mask
 *              === ====  ====        ====
 */
	.long KAHLUA_CFG_PCI_ARBITER_CNTL,  2, 0x0000,     0x9B60
	.long KAHLUA_CFG_PERF_MON_CMND_REG, 4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_PERF_MON_CNTL_REG, 2, 0x0000,     0x3F3E
	.long KAHLUA_CFG_PERF_MON_COUNTER0, 4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_PERF_MON_COUNTER1, 4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_PERF_MON_COUNTER2, 4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_PERF_MON_COUNTER3, 4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_PWR_MGT_CFG_REG,   2, 0x0000,     0x2B41
	.long KAHLUA_CFG_PWR_MGT_CFG_REG2,  1, 0x60,       0x08
	.long KAHLUA_CFG_OUTPUT_DRIVER_REG, 1, 0x05,       0xF0
	.long KAHLUA_CFG_CLOCK_DRIVER_REG,  2, 0x0000,     0x0306
	.long KAHLUA_CFG_EUMBBAR,           4, KAHLUA_EUMB_BASE, 0x0
	.long KAHLUA_CFG_MISC_REG1,         4, 0x00000000, 0xFFFFFFDF
	.long KAHLUA_CFG_MISC_REG1,         4, KAHLUA_ES_DLL_RESET, 0xFFFFFFDF
	.long KAHLUA_CFG_MISC_REG1,         4, 0x00000000, 0xFFFFFFDF

/*
 * If the bus speed is 50Mhz, the read latency is one clock off
 * and the SDRAM/memory controller will not run.  Use these default 
 * settings for a 50Mhz board.  66.66, 83.33 and 100MHz boards will
 * work with the following memory controller settings.
 * Secondly, there is at least one mv2100 that exists with memory
 * only populated at bank 1 (verses bank 0).  If this is the case,
 * the define BANK1_ONLY needs to be set.
 *
 *              reg size  data        mask
 *              === ====  ====        ====
 */
#ifdef MHZ50_RDLAT
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG1,    4, 0x31940000, 0x00600000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG2,    4, 0x06200BF4, 0x00000000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG3,    4, 0xF6200000, 0x00000000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG4,    4, 0x350C222F, 0x00A00000
#else
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG1,    4, 0x42140000, 0x00600000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG2,    4, 0x082C1001, 0x00000000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG3,    4, 0xF8300000, 0x00000000
	.long KAHLUA_CFG_MEM_CNTL_CFG_REG4,    4, 0x350C322F, 0x00A00000
#endif

	.long KAHLUA_CFG_MEM_STRT_ADR_REG,     4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_MEM_STRT_UADR_REG,    4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_EXT_MEM_STRT_ADR_REG, 4, 0x00000000, 0xFCFCFCFC
	.long KAHLUA_CFG_EXT_MEM_ST_UADR_REG,  4, 0x00000000, 0xFCFCFCFC

#ifdef BANK1_ONLY
	.long KAHLUA_CFG_MEM_END_ADR_REG,      4, 0x00001F00, 0x00000000
#else
	.long KAHLUA_CFG_MEM_END_ADR_REG,      4, 0x0000001F, 0x00000000
#endif
	.long KAHLUA_CFG_MEM_END_UADR_REG,     4, 0x00000000, 0x00000000
	.long KAHLUA_CFG_EXT_MEM_END_ADR_REG,  4, 0x00000000, 0xFCFCFCFC
	.long KAHLUA_CFG_EXT_MEM_END_UADR_REG, 4, 0x00000000, 0xFCFCFCFC

	.long KAHLUA_CFG_PAGE_MODE_CTR_TIMER,  1, 0x4C,       0x00
#ifdef BANK1_ONLY
	.long KAHLUA_CFG_MEM_BANK_ENABLE_REG,  1, 0x02,       0x00
#else
	.long KAHLUA_CFG_MEM_BANK_ENABLE_REG,  1, 0x01,       0x00
#endif
	.long KAHLUA_CFG_PROC_IF_CFG1,         4, 0x00041010, 0xFF39E483
	.long KAHLUA_CFG_PROC_IF_CFG2,         4, 0x000C000C, 0xD1F3FFF3	
	.long KAHLUA_CFG_ECC_ERROR_CTR,        1, 0x00,       0x00	
	.long KAHLUA_CFG_ECC_ERROR_TRIG,       1, 0x00,       0x00	
	.long KAHLUA_CFG_ERROR_ENABLE1,        1, 0x00,       0x00
	.long KAHLUA_CFG_ERROR_DETECT1,        1, 0xFF,       0x00
	.long KAHLUA_CFG_CPU_BUS_ERR_STAT,     1, 0xFF,       0x00
	.long KAHLUA_CFG_ERROR_ENABLE2,        1, 0x00,       0x72
	.long KAHLUA_CFG_ERROR_DETECT2,        1, 0x8D,       0x72
	.long KAHLUA_CFG_PCI_BUS_ERR_STAT,     1, 0x1F,       0xE0

	.long KAHLUA_CFG_MEM_CNTL_CFG_REG1,    4, KAHLUA_MCC1_MEMGO, 0xFFF7FFFF
	.long -1,  -1, -1,         -1		/* table end marker */


kahluaInitTableBasicPtr:
	mfspr	r21,8			/* load pointer to table */
kahluaInitBLoop:
	lwz	r3,0(r21)		/* load offset */
	lwz	r4,4(r21)		/* load size */
	lwz	r5,12(r21)		/* load mask (and-data) */
	lwz	r6,8(r21)		/* load data (or-data) */
	cmpi	0,0,r5,-1		/* table end? */
	bc	12,2,kahluaInitDone	/* if equal, yes, branch */
	bl	kahluaRegMod		/* perform register mod operation */
	addi	r21,r21,16		/* bump to next entry */
	b	kahluaInitBLoop		/* play it again sam */


kahluaInitDone:

/* exit routine, return to caller (probably start.s) */

	or	r3,r22,r22		/* return memory size in bytes */
	mtspr	8,r20			/* restore return instruction pointer */
	bclr	20,0			/* return to caller */

	.align	3


/******************************************************************************
*
* waitRefresh - delays for at least 100 microseconds.
*
* This subroutine's purpose is delay execution for at least
* 100 micro seconds to allow a memory refresh to occur
* The routine assumes the fastest mv2100 clock (400MHz).
* 400MHz = 400,000,000 Hz or clock cycles/sec 
* Decrementer counts down 1 value in 4 clock cycles.
* Want to wait 100 usecs or .0001 seconds.
*
* .CS
*     400,000,000 * .0001 = 40,000 clock cycles.
*     40,000/4 = 10000 clocks. 
* .CE
*
* registers used (and not saved):
*	r3
*
* RETURNS:
*     none
*/

	.text
	.align	3
	FUNC_BEGIN(waitRefresh)

	sync				/* ensure instructions are complete */
	eieio				/* ensures memory access is complete */

	addi	r3, r0, 10000		/* 100 us on 400MHz bus */
	mtspr   22,r3			/* set decrementer to r3 */
	sync				/* ensure instructions are complete */

refreshLoop:
        mfspr   r3,22			/* load decrementer value */
	sync				/* ensure instructions are complete */

        cmpi    0,0,r3,0
        bc      12,1,refreshLoop	/* if r3 is > 0, branch */

	bclr	20,0			/* return to caller */

	.align	3