rominit.s

VxWorks下 Mv2100的BSP源码

	addi	r4, r0, 0x1800		/* preprocessor work-around (0x8800) */
	addi	r4, r4, 0x7000		/* r4 = ICE & ICFI bit */

        mtspr   HID0, r4                /* HID0 = Enable/Inval IC */
	isync

	addi	r3, r0, 0x0800		/* r3 = ICFI bit */
	andc	r4, r4, r3		/* r4 = clear ICFI bit */

        mtspr   HID0, r4                /* HID0 = Enable IC */
	isync

        /* Wait for memory refresh to occur. */

        bl	waitRefresh

        /* 
         * Read I2C to get SPD for "real" SDRAM timing values.  
         * The I2C routines are written in 'C', so we need a stack frame.
         */

        stwu    sp,-FRAMEBASESZ(sp)     /* create an ABI stack frame */
        addi    r3,sp,8                 /* point to register image area */
	or	r22,r3,r3	        /* save structure address */

        bl      sysMemParamConfig       /* calculate memory parameters */
	or	r29,r3,r3	        /* save size */

        lwz	r8,MCCR1(r22)	        /* load r8 with mem control config 1 */
	sync				/* ensure memory access is complete */
        cmpli   0,0,r8,0		/* check for SPD error MCCR1 = 0 */
        bc	4,2,goodSpd		/* test for non-0 */

        addi    sp,sp,FRAMEBASESZ       /* remove ABI stack frame */
        b	goCEntry		/* error, leave default mem cnfg */

goodSpd:
        lwz     r9,MCCR2(r22)	        /* load mem control config 2 */
        lwz     r10,MCCR3(r22)          /* load mem control config 3 */
        lwz     r11,MCCR4(r22)          /* load mem control config 4 */

        lwz     r12,MSR3_2_1_0(r22)     /* load mem start address 3/2/1/0 */
        lwz     r13,MSR7_6_5_4(r22)     /* load mem start address 7/6/5/4 */
        lwz     r14,MSER3_2_1_0(r22)    /* load ext mem start addr 3/2/1/0 */
        lwz     r15,MSER7_6_5_4(r22)    /* load ext mem start addr 7/6/5/4 */

        lwz     r16,MER3_2_1_0(r22)     /* load mem ending addr 3/2/1/0 */
        lwz     r17,MER7_6_5_4(r22)     /* load mem ending addr 7/6/5/4 */
        lwz     r18,MEER3_2_1_0(r22)    /* load ext mem end addr 3/2/1/0 */
        lwz     r19,MEER7_6_5_4(r22)    /* load ext mem end addr 7/6/5/4 */

        lbz     r20,MPMR(r22)           /* load mem page mode */
        lbz     r21,MBER(r22)           /* load mem bank enable */

        addi    sp,sp,FRAMEBASESZ       /* remove ABI stack frame */

        /* Turn off memory controller. */

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */

	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(KAHLUA_MCC1_MEMGO)
	ori	r3,r3,LO(KAHLUA_MCC1_MEMGO)
	andc	r5,r5,r3		/* and in complement of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

	lwbrx	r5,r0,r4		/* read MCCR1 */
	addis	r3,r0,HIADJ(0x00600000) /* mask R/O bits */
	ori	r3,r3,LO(0x00600000)
	and	r5,r5,r3		/* reg5 &= reg3 */
	or	r8,r8,r5		/* reg8 |= reg5 */
	stwbrx	r8,r0,r4		/* write calculated value to MCCR1 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG2 /* add MCCR2 offset */
	stwbrx	r3,r0,r7		/* write address of MCCR2 to CAR */
	sync				/* ensure memory access is complete */

	addis	r8,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r8,r8,LO(PCI_MSTR_PRIMARY_CDR)
	stwbrx	r9,r0,r8		/* write calculated value to MCCR2 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG3 /* add MCCR3 offset */
	stwbrx	r3,r0,r7		/* write address of MCCR3 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r10,r0,r8		/* write calculated value to MCCR3 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG4 /* add MCCR4 offset */
	stwbrx	r3,r0,r7		/* write address of MCCR4 to CAR */
	sync				/* ensure memory access is complete */

	lwbrx	r5,r0,r4		/* read MCCR4 */
	addis	r3,r0,HIADJ(0x00A00000) /* mask R/O bits */
	ori	r3,r3,LO(0x00A00000)
	and	r5,r5,r3		/* reg5 &= reg3 */
	or	r11,r11,r5		/* reg11 |= reg5 */
	stwbrx	r11,r0,r8		/* write calculated value to MCCR4 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_STRT_ADR_REG /* add MSR3/2/1/0 offset */
	stwbrx	r3,r0,r7		/* write address of MSR3/2/1/0 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r12,r0,r8		/* write calc'd value to MSR3/2/1/0 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_STRT_UADR_REG /* add MSR7/6/5/4 offset */
	stwbrx	r3,r0,r7		/* write address of MSR7/6/5/4 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r13,r0,r8		/* write calc'd value to MSR7/6/5/4 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_EXT_MEM_STRT_ADR_REG /* MSER3/2/1/0 offset */
	stwbrx	r3,r0,r7		/* write addr of MSER3/2/1/0 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r14,r0,r8		/* write calc'd value to MSER3/2/1/0 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_EXT_MEM_ST_UADR_REG /* MSER7/6/5/4 offset */
	stwbrx	r3,r0,r7		/* write addr of MSER7/6/5/4 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r15,r0,r8		/* write calc'd value to MSER7/6/5/4 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_END_ADR_REG /* MER3/2/1/0 offset */
	stwbrx	r3,r0,r7		/* write addr of MER3/2/1/0 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r16,r0,r8		/* write calc'd value to MER3/2/1/0 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_END_UADR_REG /* MER7/6/5/4 offset */
	stwbrx	r3,r0,r7		/* write addr of MER7/6/5/4 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r17,r0,r8		/* write calc'd value to MER7/6/5/4 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_EXT_MEM_END_ADR_REG /* MEER3/2/1/0 offset */
	stwbrx	r3,r0,r7		/* write addr of MEER3/2/1/0 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r18,r0,r8		/* write calc'd value to MEER3/2/1/0 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_EXT_MEM_END_UADR_REG /* MEER7/6/5/4 offset */
	stwbrx	r3,r0,r7		/* write addr of MEER7/6/5/4 to CAR */
	sync				/* ensure memory access is complete */

	stwbrx	r19,r0,r8		/* write calc'd value to MEER7/6/5/4 */
	sync				/* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_PAGE_MODE_CTR_TIMER /* add page mode offset */
	stwbrx	r3,r0,r7		/* write addr of page mode to CAR */
        sync                            /* ensure memory access is complete */

        stb     r20,0(r8)               /* write page mode data to CDR */
        sync                            /* ensure memory access is complete */

	addi	r3,r6,KAHLUA_CFG_MEM_BANK_ENABLE_REG /* add mem bank enable */
        stwbrx  r3,r0,r7                /* write config. space addr. to CAR */
        sync                            /* ensure memory access is complete */

        stb     r21,0(r8)               /* write data to CDR */
        sync                            /* ensure memory access is complete */

#ifdef INCLUDE_ECC
	addi	r3,r6,KAHLUA_CFG_ERROR_ENABLE1 /* add error enable */
        stwbrx  r3,r0,r7                /* write config. space addr. to CAR */
        sync                            /* ensure memory access is complete */

        lbz     r5,0(r4)                /* read error enable register */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(KAHLUA_EE1_MEM_READ_PARITY)
	ori	r3,r3,LO(KAHLUA_EE1_MEM_READ_PARITY)
	or	r5,r5,r3		/* or in KAHLUA_EE1_MEM_READ_PARITY */
	stb	r5,0(r4)		/* write new value to error enable */
	sync				/* ensure memory access is complete */
#endif /* INCLUDE_ECC */

        /* Turn on memory controller. */

	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG1 /* MCCR1 offset */
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(KAHLUA_MCC1_MEMGO)
	ori	r3,r3,LO(KAHLUA_MCC1_MEMGO)
	or	r5,r5,r3		/* or in MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

        /* Wait for memory refresh to occur. */

        bl	waitRefresh

skipMemGo:
	/* Turn off data and instruction cache control bits */
	
	mfspr   r3, HID0
	isync
	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
	sync
	isync
	mtspr	HID0, r4		/* HID0 = r4 data/instr cache disabld */
	isync

#ifdef USER_I_CACHE_ENABLE 

	/* turn the Instruction cache ON for faster ROM access */

	mfspr   r4, HID0

	ori	r4, r4, 0x8800		/* set ICE & ICFI bit */
        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */
	isync

        /*
         * The setting of the instruction cache enable (ICE) bit must be
         * preceded by an isync instruction to prevent the cache from being
         * enabled or disabled while an instruction access is in progress.
         */
        rlwinm  r3, r4, 0, 21, 19	/* clear the ICFI bit */
        mtspr   HID0, r3                /* using 2 consec instructions */
	isync
#endif

#ifdef INCLUDE_ECC
        cmpli   0,0,r31,BOOT_COLD	/* check for warm boot */
        bc	4,2,goCEntry		/* if warm boot, skip scrub */

	/* Scrub memory and initialize ECC */

	addis	r3,r0,0x0000		/* memory starting address */
	ori	r3,r3,0x0000		/* memory starting address */
	add	r4,r3,r29		/* memory ending address + 1 */
	bl	kahluaScrub		/* (kahluaScrub) */

#endif /* INCLUDE_ECC */

goCEntry:
	/* go to C entry point */

	or	r3, r31, r31
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)

        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)

        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6
	blr


/******************************************************************************
*
* kahluaScrub - PCI configuration register modification.
*
* DESCRIPTION: kahluaScrub
*     this subroutine's purpose is to initialize (i.e., scrub)
*     DRAM, the KAHLUA ASIC protects DRAM by utilizing ECC, so
*     the scrub insures that the entire DRAM array's check bits
*     are initialized to a known state
*
*     kahluaScrub(start-address, end-address, control-flag);
*     r1	= don't care, no stack is needed
*     r3	= starting address of DRAM
*     r4	= ending address of DRAM (plus 1)
*     spr8	= return program counter
*
* RETURNS:
*     r3	= 1, DRAM ECC error detected
*    		= 0, no DRAM ECC errors occurred
*/

	.data
	.align	3
	DATA_EXPORT(kahluaScrubData)
kahluaScrubData:
	.long	0x00000000, 0x00000000

	.text
	.align	3
	FUNC_EXPORT(kahluaScrub)
kahluaScrub:
	mfspr	r16,8			/* save return instruction pointer */
	or	r13,r3,r3		/* save argument #1 */
	or	r14,r4,r4		/* save argument #2 */
	addis	r0,r0,0			/* insure r0 is zero */
	ori	r0,r0,0			/* insure r0 is zero */

        /* load 64-bit number to initialize memory with */

	addis	r6,r0,HI(kahluaScrubData)
	ori	r6,r6,LO(kahluaScrubData)
/*
 * setup loop specifics
 *
 * attempt a fpu register access only if kahlua has fpu enabled,
 * based on HID1 bit 0 being a 1 or 0.  0 = FPU enabled, 1 = FPU disabled
 */

	mfspr	r5,1009			/* load hid1 contents */
	andi.	r5,r5,0x0001		/* extract FPU available bit and test */
	bc	4,2,kahluaFpuDisabled	/* if 1, don't load FPU register */

	lfdu	0,0(r6)
	subf	r18,r13,r14		/* calculate number of bytes */
	rlwinm	r18,r18,29,3,31		/* calculate number of doubles */
	addi	r17,r13,-8		/* starting address munged */
	mtspr	9,r18			/* load number of doubles/words */
	b	kahluaScrubLoopFpu