rominit.s

VxWorks下 Mv2100的BSP源码

/* romInit.s - Motorola MVME2100 ROM initialization module */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01k,25apr02,dat  SPR 65967, 400Mhz CPU speeds
01j,03jan02,mil  Cleaned up build errors on kahluaDefInit and waitRefresh.
01i,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
01h,20Oct99,rhk  Toggle the DLL_RESET bit in the Emulation Support 
		 Configuration register after a reset to prevent
		 loss of SDRAM clock output (Errata Version 2.0,
		 item #9 10/07/99).
01g,24jun99,srr  if warm reboot, skip memory controller init.
01f,06may99,dmw  added soldered/socket ROM support.
01e,16apr99,rhk  added code to allow switch to PReP mode.
01d,26mar99,dmw  added SPD parsing for memory controller settings.
01c,19feb99,srr  clear MEMGO bit before memory controller init incase
                 we are doing a warm reboot and MEMGO is already set.
01b,07jan99,srr  changed startType save register to r31 (non-volatile).
01a,14dec98,srr  created. (from mv2603/romInit.s, ver 01m)
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"	

	/* Exported internal functions */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */

	/* externals */

	.extern romStart	/* system initialization routine */
        .extern sysMemParamConfig /* memory parameter initialization */

        .set	MCCR1,0
        .set    MCCR2,MCCR1+4
        .set    MCCR3,MCCR2+4
        .set    MCCR4,MCCR3+4

        .set    MSR3_2_1_0,MCCR4+4
        .set    MSR7_6_5_4,MSR3_2_1_0+4
        .set    MSER3_2_1_0,MSR7_6_5_4+4
        .set    MSER7_6_5_4,MSER3_2_1_0+4

        .set    MER3_2_1_0,MSER7_6_5_4+4
        .set    MER7_6_5_4,MER3_2_1_0+4
        .set    MEER3_2_1_0,MER7_6_5_4+4
        .set    MEER7_6_5_4,MEER3_2_1_0+4

        .set    MPMR,MEER7_6_5_4+4
        .set    MBER,MPMR+1

	.text
	.align 2

		
/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )
*/

_romInit:
romInit:

	bl	cold
	
	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1999 Wind River Systems, Inc."
	.align 2

cold:
	li	r31, BOOT_COLD
	bl	start		/* skip over next instruction */

			
warm:
	or	r31, r3, r3	/* startType to r31 */

start:
	/* identify execution point as far as socketed or soldered. */

	bl	lreg			/* br below. load link reg w/ eaddr */
lreg:
	mfspr	r3,8			/* copy current instruction address */
	rlwinm	r3,r3,16,16,31		/* r3 = ((r3 >> 16) & 0x0000FFFF)   */
	cmpli	0,0,r3,0xFF80		/* If flash address (< 0xff800000), */
	bc	12,0,romExecution	/* proceed to flash image */

	/* check bit 0 of software configuration header */

	addis	r3,r0,HIADJ(MV2100_CONFIG_HDR_REG) /* load S/W header reg */
	ori	r3,r3,LO(MV2100_CONFIG_HDR_REG)

	xor     r4,r4,r4		/* clear r4 */
        lbz	r4,0(r3)		/* read S/W readbale header register */
	sync				/* ensure memory access is complete */
	andi.	r4,r4,1			/* mask Socketed/Soldered bit */
	cmpli	0,0,r4,1		/* Jumper is out (1) */
	bc	12,2,romExecution	/* if 1, socketed (ROM) execution */

	/* else, branch to soldered flash */

        addis	r3,r0,HIADJ(FLASH_TEXT_ADRS)	/* Flash address */
        ori	r3,r3,LO(FLASH_TEXT_ADRS)
	mtspr	8,r3
	sync				/* ensure memory access is complete */
	bclr    0x14,0x0		/* branch via the link register */

romExecution:
	/* Zero-out registers: r0 & SPRGs */

	xor     r0,r0,r0
	mtspr   272,r0
	mtspr   273,r0
	mtspr   274,r0
	mtspr   275,r0

        /* initialize the stack pointer */

        lis     sp, HI(STACK_ADRS)
        ori     sp, sp, LO(STACK_ADRS)

	/*
	 *	Set HID0 to a known state
	 *	Enable machine check input pin (EMCP) for DRAM ECC detection
	 */

	addis   r3,r0,0x8000
	ori     r3,r3,0x0000
	mtspr   HID0, r3

	xor     r3, r3, r3		/* clear r3 */

#ifndef CHRP_ADRS_MAP
	/* switch to PReP mode, always come up by default as CHRP */

	addis   r3,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori     r3,r3,LO(CNFG_PCI_HOST_BRDG)
	addi    r3,r3,KAHLUA_CFG_PROC_IF_CFG1  /* Proc IF Config 1 reg offset */
	addis   r4,r0,HIADJ(PCI_CHRP_PRIMARY_CAR) /* use the CHRP CAR address*/
	ori     r4,r4,LO(PCI_CHRP_PRIMARY_CAR)
	stwbrx  r3,r0,r4		/* write address of PIC1 reg. */
	eieio
	sync
	addis   r4,r0,HIADJ(PCI_CHRP_PRIMARY_CDR) /* use the CHRP CDR address*/
	ori     r4,r4,LO(PCI_CHRP_PRIMARY_CDR)
	lwbrx   r5,r0,r4		/* get value of PIC1 register */
	eieio
	sync
	addis   r3,r0,HIADJ(KAHLUA_PIC1_ADDRESS_MAP)	/* set PReP mode bit */
	ori     r3,r3,LO(KAHLUA_PIC1_ADDRESS_MAP)
	or	r5,r5,r3		/* OR with current PIC 1 reg value */
	stwbrx  r5,r0,r4		/* write value back to PIC1 reg */
	eieio				/* give it time to switch */
	sync				/* now in PReP mode */
#endif /* not CHRP_ADRS_MAP */

	/* Turn on FPU if enabled and available */

        mfspr   r3, 1009		/* load hid1 contents */
        andi.   r3, r3, 0x0001		/* extract FPU available bit and test */
        bc      4,2,skipFpuInit		/* if not equal, then we have no FPU */
	xor     r3, r3, r3		/* clear r3 */
        ori     r3, r3, 0x2000		/* set FP */
        isync				/* synchronize */
        mtmsr   r3			/* set machine state register */
        isync				/* synchronize */

	/* Init the floating point control/status register */

	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize the floating point data regsiters to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync
        b       dontTurnOffFP
skipFpuInit:

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn off FP
	 */

	andi.	r3, r3, 0
	isync
	mtmsr 	r3
	isync

dontTurnOffFP:
	/* Init the Segment registers */

	andi.	r3, r3, 0
	isync
	mtsr    0,r3
	isync
	mtsr    1,r3
	isync
	mtsr    2,r3
	isync
	mtsr    3,r3
	isync
	mtsr    4,r3
	isync
	mtsr    5,r3
	isync
	mtsr    6,r3
	isync
	mtsr    7,r3
	isync
	mtsr    8,r3
	isync
	mtsr    9,r3
	isync
	mtsr    10,r3
	isync
	mtsr    11,r3
	isync
	mtsr    12,r3
	isync
	mtsr    13,r3
	isync
	mtsr    14,r3
	isync
	mtsr    15,r3
	isync

	cmpli   0,0,r31,BOOT_COLD	/* check for warm boot */
	bc	4,2,skipMemGo		/* if warm boot, skip mem cntlr init */

	/* Clear MEMGO in MCCR1 so we can make memory controller adjustments. */

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,KAHLUA_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */
	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(KAHLUA_MCC1_MEMGO)
	ori	r3,r3,LO(KAHLUA_MCC1_MEMGO)
	andc	r5,r5,r3		/* and in complement of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

        /* 
         * Configure the memory controller in a default setting so that
         * we can create a stack and read the SPD/VPD data.
         */

	bl	kahluaDefInit		/* (kahluaDefInit) */

	/* Enable Instruction Cache */

	mfspr   r4, HID0		/* r4 = default */

	isync