universe.h

VxWorks下 Mv2100的BSP源码

#define L_CMDERR_L_ENABLE       (1 << 23)       /* Clear and Enable Logging   */

/* DMA Transfer Control Register */

#define DCTL_VALID_BITS_MASK	0x80c7f180
#define DCTL_MASK               0x7f380e7f      /* Reserved bits */
#define DCTL_L2V                (1 << 31)       /* PCI-to-VME transfer */
#define DCTL_L2V_MSK		(1 << 31)
#define DCTL_VDW_MSK		(3 << 22)
#define DCTL_VAS_MSK		(7 << 16)
#define DCTL_PGM_MSK		(3 << 14)
#define DCTL_SUPER_MSK		(3 << 12)
#define DCTL_VCT_MSK		(1 << 8)
#define DCTL_LD64EN_MSK		(1 << 7)
#define DCTL_L2V_VME_PCI	(0)		/* VME-to-PCI transfer */
#define DCTL_L2V_PCI_VME	(1 << 31)       /* PCI-to-VME transfer */
#define DCTL_VDW_8              (0)             /* Maximum data width 8 bits */
#define DCTL_VDW_16             (1 << 22)       /* Maximum data width 16 bits */
#define DCTL_VDW_32             (2 << 22)       /* Maximum data width 32 bits */
#define DCTL_VDW_64             (3 << 22)       /* Maximum data width 64 bits */
#define DCTL_VAS_A16            (0)             /* VME address space A16 */
#define DCTL_VAS_A24            (1 << 16)       /* VME address space A24 */
#define DCTL_VAS_A32            (2 << 16)       /* VME address space A32 */
#define DCTL_VAS_USER1          (6 << 16)       /* VME address space User1 */
#define DCTL_VAS_USER2          (7 << 16)       /* VME address space User2 */
#define DCTL_PGM_DATA           (0)             /* Data AM code */
#define DCTL_PGM_PRGM           (1 << 14)       /* Program AM code */
#define DCTL_SUPER_USER         (0)             /* Non-privileged AM code */
#define DCTL_SUPER_SUP          (1 << 12)       /* Supervisor AM code */
#define DCTL_VCT_EN             (1 << 8)        /* Block mode capable */
#define DCTL_VCT_SINGLE		0		/* Single cycle only */
#define DCTL_VCT_BLK		(1 << 8)        /* Single and Block transfers */
#define DCTL_LD64EN             (1 << 7)        /* 64-bit PCI transactions */
#define DCTL_LD64EN_32		0		/* 32-bit PCI transactions */

/* DMA Transfer Byte Count Register */

#define DTBC_MASK       0xff000000
#define	DTBC_VALID_BITS_MASK	0x00ffffff

/* DMA General Control/Status Register */

#define DGCS_MASK               0x00800000      /* Reserved bits */
#define DGCS_VALID_BITS_MASK	0xe87fef6f
#define DGCS_CHAIN_MSK		(1 << 27)
#define DGCS_VON_MSK		(0x7 << 20)
#define DGCS_VOFF_MSK		(0xf << 16)
#define DGCS_STATUS_MSK		(0xef << 8)
#define DGCS_INTR_MSK		(0x6f << 0)
#define DGCS_GO                 (1 << 31)       /* Start DMA */
#define DGCS_STOP_REQ           (1 << 30)       /* Stop Request */
#define DGCS_HALT_REQ           (1 << 29)       /* Halt Request */
#define DGCS_CHAIN_DMODE	(0)		/* DMA Direct Mode */
#define DGCS_CHAIN_LLMODE       (1 << 27)       /* DMA Linked List Mode */
#define DGCS_CHAIN              (1 << 27)       /* DMA chaining */
#define DGCS_VON_DONE           (0)             /* Transfer count until done*/
#define DGCS_VON_256            (1 << 20)       /* Transfer count 256 bytes */
#define DGCS_VON_512            (2 << 20)       /* Transfer count 512 bytes */
#define DGCS_VON_1024           (3 << 20)       /* Transfer count 1024 bytes */
#define DGCS_VON_2048           (4 << 20)       /* Transfer count 2048 bytes */
#define DGCS_VON_4096           (5 << 20)       /* Transfer count 4096 bytes */
#define DGCS_VON_8192           (6 << 20)       /* Transfer count 4096 bytes */
#define DGCS_VON_16384          (7 << 20)       /* Transfer count 16384 bytes */
#define DGCS_VOFF_0             (0)             /* Time off VME bus0 us */
#define DGCS_VOFF_16            (1 << 16)       /* Time off VME bus16 us */
#define DGCS_VOFF_32            (2 << 16)       /* Time off VME bus32 us */
#define DGCS_VOFF_64            (3 << 16)       /* Time off VME bus64 us */
#define DGCS_VOFF_128           (4 << 16)       /* Time off VME bus128 us */
#define DGCS_VOFF_256           (5 << 16)       /* Time off VME bus256 us */
#define DGCS_VOFF_512           (6 << 16)       /* Time off VME bus512 us */
#define DGCS_VOFF_1024          (7 << 16)       /* Time off VME bus1024 us */
#define DGCS_ACT                (1 << 15)       /* DMA active */
#define DGCS_STOP               (1 << 14)       /* DMA stopped */
#define DGCS_HALT               (1 << 13)       /* DMA halted */
#define DGCS_DONE               (1 << 11)       /* DMA done */
#define DGCS_LERR               (1 << 10)       /* PCI bus error */
#define DGCS_VERR               (1 << 9)        /* VME bus error */
#define DGCS_P_ERR              (1 << 8)        /* Protocol error */
#define DGCS_INT_STOP           (1 << 6)        /* Interrupt stop enable */
#define DGCS_INT_HALT           (1 << 5)        /* Interrupt halt enable */
#define DGCS_INT_DONE           (1 << 3)        /* Interrupt done enable */
#define DGCS_INT_LERR           (1 << 2)        /* Interrupt LERR enable */
#define DGCS_INT_VERR           (1 << 1)        /* Interrupt VERR enable */
#define DGCS_INT_P_ERR          (1)             /* Interrupt protocol enable */

/* DMA Linked List Update Enable Register */

/* PCI Configuration Base Address Register */

#define PCI_BS_SPACE            (1)             /* Memory or I/O power-up */

/* PCI Interrupt Enable Register */

#define LINT_EN_MASK            0xff000800      /* Reserved bits */
#define LINT_EN_LM3		0x00800000	/* Enable Interrupt loc mon 3 */
#define LINT_EN_LM2             0x00400000      /* Enable Interrupt loc mon 2 */
#define LINT_EN_LM1             0x00200000      /* Enable Interrupt loc mon 1 */
#define LINT_EN_LM0             0x00100000      /* Enable Interrupt loc mon 0 */
#define LINT_EN_MBOX3		0x00080000	/* Enable Interrupt mailbox 3 */
#define LINT_EN_MBOX2           0x00040000      /* Enable Interrupt mailbox 2 */
#define LINT_EN_MBOX1           0x00020000      /* Enable Interrupt mailbox 1 */
#define LINT_EN_MBOX0           0x00010000      /* Enable Interrupt mailbox 0 */
#define LINT_EN_ACFAIL          0x00008000      /* Enable Interrupt ACFAIL   */
#define LINT_EN_SYSFAIL         0x00004000      /* Enable Interrupt SYSFAIL  */
#define LINT_EN_SW_INT          0x00002000      /* Enable Interrupt SW_INT   */
#define LINT_EN_SW_IACK         0x00001000      /* Enable Interrupt SW_ACK   */
#define LINT_EN_VERR            0x00000400      /* Enable Interrupt ACFAIL   */
#define LINT_EN_LERR            0x00000200      /* Enable Interrupt ACFAIL   */
#define LINT_EN_DMA             0x00000100      /* Enable Interrupt ACFAIL   */
#define LINT_EN_VIRQ7           0x00000080      /* Enable Interrupt VME IRQ7 */
#define LINT_EN_VIRQ6           0x00000040      /* Enable Interrupt VME IRQ6 */
#define LINT_EN_VIRQ5           0x00000020      /* Enable Interrupt VME IRQ5 */
#define LINT_EN_VIRQ4           0x00000010      /* Enable Interrupt VME IRQ4 */
#define LINT_EN_VIRQ3           0x00000008      /* Enable Interrupt VME IRQ3 */
#define LINT_EN_VIRQ2           0x00000004      /* Enable Interrupt VME IRQ2 */
#define LINT_EN_VIRQ1           0x00000002      /* Enable Interrupt VME IRQ1 */
#define LINT_EN_VOWN            0x00000001      /* Enable Interrupt VME OWN */

/* PCI Interrupt Status Register */

#define LINT_STAT_MASK          0xff000800      /* Reserved bits */
#define LINT_STAT_LM3           0x00800000      /* Status Interrupt loc mon 3 */
#define LINT_STAT_LM2           0x00400000      /* Status Interrupt loc mon 2 */
#define LINT_STAT_LM1           0x00200000      /* Status Interrupt loc mon 1 */
#define LINT_STAT_LM0           0x00100000      /* Status Interrupt loc mon 0 */
#define LINT_STAT_MBOX3         0x00080000      /* Status Interrupt mailbox 3 */
#define LINT_STAT_MBOX2         0x00040000      /* Status Interrupt mailbox 2 */
#define LINT_STAT_MBOX1         0x00020000      /* Status Interrupt mailbox 1 */
#define LINT_STAT_MBOX0         0x00010000      /* Status Interrupt mailbox 0 */
#define LINT_STAT_ACFAIL        (1 << 15)       /* Status Interrupt ACFAIL   */
#define LINT_STAT_SYSFAIL       (1 << 14)       /* Status Interrupt SYSFAIL  */
#define LINT_STAT_SW_INT        (1 << 13)       /* Status Interrupt SW_INT   */
#define LINT_STAT_SW_IACK       (1 << 12)       /* Status Interrupt SW_ACK   */
#define LINT_STAT_VERR          (1 << 10)       /* Status Interrupt ACFAIL   */
#define LINT_STAT_LERR          (1 << 9)        /* Status Interrupt ACFAIL   */
#define LINT_STAT_DMA           (1 << 8)        /* Status Interrupt ACFAIL   */
#define LINT_STAT_VIRQ7         (1 << 7)        /* Status Interrupt VME IRQ7 */
#define LINT_STAT_VIRQ6         (1 << 6)        /* Status Interrupt VME IRQ6 */
#define LINT_STAT_VIRQ5         (1 << 5)        /* Status Interrupt VME IRQ5 */
#define LINT_STAT_VIRQ4         (1 << 4)        /* Status Interrupt VME IRQ4 */
#define LINT_STAT_VIRQ3         (1 << 3)        /* Status Interrupt VME IRQ3 */
#define LINT_STAT_VIRQ2         (1 << 2)        /* Status Interrupt VME IRQ2 */
#define LINT_STAT_VIRQ1         (1 << 1)        /* Status Interrupt VME IRQ1 */
#define LINT_STAT_VOWN          (1 << 0)        /* Status Interrupt VME OWN */

#define LINT_STAT_CLEAR		0x00fff7ff	/* clear all interrupts */
#define LINT_STAT_INT_MASK	0x00fff7ff	/* mask received interrupts */
#define LINT_STAT_FAIL_MASK     0x0000c000      /* mask for sysfail,acfail */

/* PCI Interrupt MAP Register 0 */

#define LINT_MAP0_MASK  0x77777777

/* PCI Interrupt MAP Register 1 */

#define LINT_MAP1_MASK  0x77770777

/* PCI Interrupt MAP Register 2 */

#define LINT_MAP2_MASK  0x77777777

/* VMEbus Interrupt Enable Register */

#define VINT_EN_MASK            0xfe0f17ff
#define VINT_EN_VME_SW7         (1 << 31)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW6         (1 << 30)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW5         (1 << 29)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW4         (1 << 28)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW3         (1 << 27)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW2         (1 << 26)       /* generate interrupt - U2 */
#define VINT_EN_VME_SW1         (1 << 25)       /* generate interrupt - U2 */
#define VINT_EN_MBOX3		(1 << 19)	/* Mailbox 3 VME intr enable */
#define VINT_EN_MBOX2           (1 << 18)       /* Mailbox 2 VME intr enable */
#define VINT_EN_MBOX1           (1 << 17)       /* Mailbox 1 VME intr enable */
#define VINT_EN_MBOX0           (1 << 16)       /* Mailbox 0 VME intr enable */
#define VINT_EN_SW_INT          (1 << 12)       /* SW_INT interrupt generate */
#define VINT_EN_VERR            (1 << 10)       /* VERR interrupt generate */
#define VINT_EN_LERR            (1 << 9)        /* LERR enable */
#define VINT_EN_DMA             (1 << 8)        /* DMA enable */
#define VINT_EN_LINT7           (1 << 7)        /* LINT7 enable */
#define VINT_EN_LINT6           (1 << 6)        /* LINT6 enable */
#define VINT_EN_LINT5           (1 << 5)        /* LINT5 enable */
#define VINT_EN_LINT4           (1 << 4)        /* LINT4 enable */
#define VINT_EN_LINT3           (1 << 3)        /* LINT3 enable */
#define VINT_EN_LINT2           (1 << 2)        /* LINT2 enable */
#define VINT_EN_LINT1           (1 << 1)        /* LINT1 enable */
#define VINT_EN_LINT0           (1)             /* LINT0 enable */

/* VMEbus Interrupt Status Register */

#define VINT_STAT_MASK          0xfe0f17ff
#define VINT_STAT_VME_SW7       (1 << 31)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW6       (1 << 30)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW5       (1 << 29)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW4       (1 << 28)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW3       (1 << 27)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW2       (1 << 26)       /* interrupt active - U2 */
#define VINT_STAT_VME_SW1       (1 << 25)       /* interrupt active - U2 */
#define VINT_STAT_MBOX3         (1 << 19)       /* Mailbox 3 VME intr status */
#define VINT_STAT_MBOX2         (1 << 18)       /* Mailbox 2 VME intr status */
#define VINT_STAT_MBOX1         (1 << 17)       /* Mailbox 1 VME intr status */
#define VINT_STAT_MBOX0         (1 << 16)       /* Mailbox 0 VME intr status */
#define VINT_STAT_SW_INT        (1 << 12)       /* SW_INT interrupt active */
#define VINT_STAT_VERR          (1 << 10)       /* VERR interrupt active */
#define VINT_STAT_LERR          (1 << 9)        /* LERR interrupt active */
#define VINT_STAT_DMA           (1 << 8)        /* DMA interrupt active */
#define VINT_STAT_LINT7         (1 << 7)        /* LINT7 interrupt active */
#define VINT_STAT_LINT6         (1 << 6)        /* LINT6 interrupt active */
#define VINT_STAT_LINT5         (1 << 5)        /* LINT5 interrupt active */
#define VINT_STAT_LINT4         (1 << 4)        /* LINT4 interrupt active */
#define VINT_STAT_LINT3         (1 << 3)        /* LINT3 interrupt active */
#define VINT_STAT_LINT2         (1 << 2)        /* LINT2 interrupt active */
#define VINT_STAT_LINT1         (1 << 1)        /* LINT1 interrupt active */
#define VINT_STAT_LINT0         (1)             /* LINT0 interrupt active */

#define VINT_STAT_CLEAR		0x17ff		/* clear outgoing VME intrs. */

/* VMEbus Interrupt Map Register 0 */

#define VINT_MAP0_MASK          0x77777777
#define VINT_MAP0_MAPPING	0x76543210

/* VMEbus Interrupt Map Register 1 */

#define VINT_MAP1_MASK          0x00070777
#define VINT_MAP1_DMA_MASK      0x00000007
#define VINT_MAP1_LERR_MASK	0x00000070
#define VINT_MAP1_VERR_MASK	0x00000700
#define VINT_MAP1_SW_INT_MASK	0x00070000
#define VINT_MAP1_DMA_LVL_1     0x01
#define VINT_MAP1_DMA_LVL_2     0x02
#define VINT_MAP1_DMA_LVL_3     0x03
#define VINT_MAP1_DMA_LVL_4     0x04
#define VINT_MAP1_DMA_LVL_5     0x05
#define VINT_MAP1_DMA_LVL_6     0x06
#define VINT_MAP1_DMA_LVL_7     0x07

/* VMEbus Interrupt Map Register 2 */

#define VINT_MAP2_MASK          0x00007777

/* VMEbus Interrupt Status/ID Out Register */

#define STATID_MASK             0x1ffffff

/* VMEbus IRQ1 Status/ID Register */

#define V1_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ2 Status/ID Register */

#define V2_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ3 Status/ID Register */

#define V3_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ4 Status/ID Register */

#define V4_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ5 Status/ID Register */

#define V5_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ6 Status/ID Register */

#define V6_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus IRQ7 Status/ID Register */

#define V7_STATID_ERR           (1 << 8)        /* Bus Error during IACK     */

/* VMEbus Master Control Register */