universe.h

VxWorks下 Mv2100的BSP源码

 */

#define UNIVERSE_SCYC_ADDR      UNIV_ADRS(0x174)

/* Special Cycle Bit Enable Mask                   0x178   31-00 */

#define UNIVERSE_SCYC_EN        UNIV_ADRS(0x178)

/* Special Cycle Compare Register                  0x178   31-00 */

#define UNIVERSE_SCYC_CMP       UNIV_ADRS(0x17c)

/* Special Cycle Swap Register                     0x178   31-00 */

#define UNIVERSE_SCYC_SWP       UNIV_ADRS(0x180)

/* Other Registers */

#define UNIVERSE_LMISC          UNIV_ADRS(0x184)
#define UNIVERSE_SLSI           UNIV_ADRS(0x188)
#define UNIVERSE_L_CMDERR       UNIV_ADRS(0x18c)
#define UNIVERSE_LAERR          UNIV_ADRS(0x190)
#define UNIVERSE_LSI4_CTL	UNIV_ADRS(0x1a0) /* local slave image 4 cntrl */
#define UNIVERSE_LSI4_BS	UNIV_ADRS(0x1a4) /* lcl slv image 4 base addr */
#define UNIVERSE_LSI4_BD	UNIV_ADRS(0x1a8) /* lcl slv image 4 bound adr */
#define UNIVERSE_LSI4_TO	UNIV_ADRS(0x1ac) /* LSI 4 translation offset */
#define UNIVERSE_LSI5_CTL       UNIV_ADRS(0x1b4) /* local slave image 5 cntrl */
#define UNIVERSE_LSI5_BS        UNIV_ADRS(0x1b8) /* lcl slv image 5 base addr */
#define UNIVERSE_LSI5_BD        UNIV_ADRS(0x1bc) /* lcl slv image 5 bound adr */
#define UNIVERSE_LSI5_TO        UNIV_ADRS(0x1c0) /* LSI 5 translation offset */
#define UNIVERSE_LSI6_CTL       UNIV_ADRS(0x1c8) /* local slave image 6 cntrl */
#define UNIVERSE_LSI6_BS        UNIV_ADRS(0x1cc) /* lcl slv image 6 base addr */
#define UNIVERSE_LSI6_BD        UNIV_ADRS(0x1d0) /* lcl slv image 6 bound adr */
#define UNIVERSE_LSI6_TO        UNIV_ADRS(0x1d4) /* LSI 6 translation offset */
#define UNIVERSE_LSI7_CTL       UNIV_ADRS(0x1dc) /* local slave image 7 cntrl */
#define UNIVERSE_LSI7_BS        UNIV_ADRS(0x1e0) /* lcl slv image 7 base addr */
#define UNIVERSE_LSI7_BD        UNIV_ADRS(0x1e4) /* lcl slv image 7 bound adr */
#define UNIVERSE_LSI7_TO        UNIV_ADRS(0x1e8) /* LSI 7 translation offset */
#define UNIVERSE_DCTL           UNIV_ADRS(0x200)
#define UNIVERSE_DTBC           UNIV_ADRS(0x204)
#define UNIVERSE_DLA            UNIV_ADRS(0x208)
#define UNIVERSE_DVA            UNIV_ADRS(0x210)
#define UNIVERSE_DCPP           UNIV_ADRS(0x218)
#define UNIVERSE_DGCS           UNIV_ADRS(0x220)
#define UNIVERSE_D_LLUE         UNIV_ADRS(0x224)
#define UNIVERSE_LINT_EN        UNIV_ADRS(0x300)
#define UNIVERSE_LINT_STAT      UNIV_ADRS(0x304)
#define UNIVERSE_LINT_MAP0      UNIV_ADRS(0x308)
#define UNIVERSE_LINT_MAP1      UNIV_ADRS(0x30C)
#define UNIVERSE_VINT_EN        UNIV_ADRS(0x310)
#define UNIVERSE_VINT_STAT      UNIV_ADRS(0x314)
#define UNIVERSE_VINT_MAP0      UNIV_ADRS(0x318)
#define UNIVERSE_VINT_MAP1      UNIV_ADRS(0x31C)
#define UNIVERSE_STATID         UNIV_ADRS(0x320)
#define UNIVERSE_V1_STATID      UNIV_ADRS(0x324)
#define UNIVERSE_V2_STATID      UNIV_ADRS(0x328)
#define UNIVERSE_V3_STATID      UNIV_ADRS(0x32C)
#define UNIVERSE_V4_STATID      UNIV_ADRS(0x330)
#define UNIVERSE_V5_STATID      UNIV_ADRS(0x334)
#define UNIVERSE_V6_STATID      UNIV_ADRS(0x338)
#define UNIVERSE_V7_STATID      UNIV_ADRS(0x33C)
#define UNIVERSE_LINT_MAP2	UNIV_ADRS(0x340) /* local interrupt Map 2 reg */
#define UNIVERSE_VINT_MAP2	UNIV_ADRS(0x344) /* VME interrupt Map 2 reg */
#define UNIVERSE_MBOX0		UNIV_ADRS(0x348) /* mailbox 0 */
#define UNIVERSE_MBOX1		UNIV_ADRS(0x34c) /* mailbox 1 */
#define UNIVERSE_MBOX2		UNIV_ADRS(0x350) /* mailbox 2 */
#define UNIVERSE_MBOX3		UNIV_ADRS(0x354) /* mailbox 3 */
#define UNIVERSE_SEMA0		UNIV_ADRS(0x358) /* semaphore 0 register */
#define UNIVERSE_SEMA1          UNIV_ADRS(0x35c) /* semaphore 1 register */
#define UNIVERSE_MAST_CTL       UNIV_ADRS(0x400)
#define UNIVERSE_MISC_CTL       UNIV_ADRS(0x404)
#define UNIVERSE_MISC_STAT      UNIV_ADRS(0x408)
#define UNIVERSE_USER_AM        UNIV_ADRS(0x40C)
#define UNIVERSE_VSI0_CTL       UNIV_ADRS(0xF00)
#define UNIVERSE_VSI0_BS        UNIV_ADRS(0xF04)
#define UNIVERSE_VSI0_BD        UNIV_ADRS(0xF08)
#define UNIVERSE_VSI0_TO        UNIV_ADRS(0xF0C)
#define UNIVERSE_VSI1_CTL       UNIV_ADRS(0xF14)
#define UNIVERSE_VSI1_BS        UNIV_ADRS(0xF18)
#define UNIVERSE_VSI1_BD        UNIV_ADRS(0xF1C)
#define UNIVERSE_VSI1_TO        UNIV_ADRS(0xF20)
#define UNIVERSE_VSI2_CTL       UNIV_ADRS(0xF28)
#define UNIVERSE_VSI2_BS        UNIV_ADRS(0xF2C)
#define UNIVERSE_VSI2_BD        UNIV_ADRS(0xF30)
#define UNIVERSE_VSI2_TO        UNIV_ADRS(0xF34)
#define UNIVERSE_VSI3_CTL       UNIV_ADRS(0xF3C)
#define UNIVERSE_VSI3_BS        UNIV_ADRS(0xF40)
#define UNIVERSE_VSI3_BD        UNIV_ADRS(0xF44)
#define UNIVERSE_VSI3_TO        UNIV_ADRS(0xF48)
#define UNIVERSE_LM_CTL		UNIV_ADRS(0xF64) /* location mon. control */
#define UNIVERSE_LM_BS		UNIV_ADRS(0xF68) /* loc. mon. base address */
#define UNIVERSE_VRAI_CTL       UNIV_ADRS(0xF70)
#define UNIVERSE_VRAI_BS        UNIV_ADRS(0xF74)
#define UNIVERSE_VCSR_CTL       UNIV_ADRS(0xF80)
#define UNIVERSE_VCSR_TO        UNIV_ADRS(0xF84)
#define UNIVERSE_V_AMERR        UNIV_ADRS(0xF88)
#define UNIVERSE_VAERR          UNIV_ADRS(0xF8C)
#define UNIVERSE_VSI4_CTL       UNIV_ADRS(0xF90)
#define UNIVERSE_VSI4_BS        UNIV_ADRS(0xF94)
#define UNIVERSE_VSI4_BD        UNIV_ADRS(0xF98)
#define UNIVERSE_VSI4_TO        UNIV_ADRS(0xF9c)
#define UNIVERSE_VSI5_CTL       UNIV_ADRS(0xFa4)
#define UNIVERSE_VSI5_BS        UNIV_ADRS(0xFa8)
#define UNIVERSE_VSI5_BD        UNIV_ADRS(0xFac)
#define UNIVERSE_VSI5_TO        UNIV_ADRS(0xFb0)
#define UNIVERSE_VSI6_CTL       UNIV_ADRS(0xFb8)
#define UNIVERSE_VSI6_BS        UNIV_ADRS(0xFbc)
#define UNIVERSE_VSI6_BD        UNIV_ADRS(0xFc0)
#define UNIVERSE_VSI6_TO        UNIV_ADRS(0xFc4)
#define UNIVERSE_VSI7_CTL       UNIV_ADRS(0xFcc)
#define UNIVERSE_VSI7_BS        UNIV_ADRS(0xFd0)
#define UNIVERSE_VSI7_BD        UNIV_ADRS(0xFd4)
#define UNIVERSE_VSI7_TO        UNIV_ADRS(0xFd8)
#define UNIVERSE_VCSR_CLR       UNIV_ADRS(0xFF4)
#define UNIVERSE_VCSR_SET       UNIV_ADRS(0xFF8)
#define UNIVERSE_VCSR_BS        UNIV_ADRS(0xFFC)

/* NOW LET'S DEFINE THE BITS FOR THESE REGISTERS */

/* PCI MISC0 Register */

#define PCI_MISC0_LATENCY_TIMER 0x0000f800      /* max. value for timer */

/* PCI Configuration Space Control and Status Register */

#define PCI_CSR_MASK            0x007ffc00      /* Reserved bits */
#define PCI_CSR_D_PE            (1 << 31)       /* Detected/Clear Parity Error*/
#define PCI_CSR_S_SERR          (1 << 30)       /* Signalled SERR#            */
#define PCI_CSR_R_MA            (1 << 29)       /* Received Master Abort      */
#define PCI_CSR_R_TA            (1 << 28)       /* Received Target Abort      */
#define PCI_CSR_S_TA            (1 << 27)       /* Signalled Target Abort     */
#define PCI_CSR_DEVSEL_MEDIUM   (1 << 25)       /* Universe is medium speed   */
#define PCI_CSR_DP_D            (1 << 24)       /* Master detected/generated  */
                                                /* a data parity error        */
#define PCI_CSR_TFBBC           (1 << 23)       /* Target Fast Back to Back   */
                                                /* Capable (must be ?)        */
#define PCI_CSR_MFBBC           (1 << 9)        /* Master Fast Back to Back   */
                                                /* Capable (must be 0)        */
#define PCI_CSR_SERR_EN         (1 << 8)        /* Enable SERR# drivers       */
#define PCI_CSR_WAIT            (1 << 7)        /* Wait Cycle Control         */
#define PCI_CSR_PERSP           (1 << 6)        /* Enable Parity Error Resp   */
#define PCI_CSR_VGAPS           (1 << 5)        /* VGA Palette Snp (must be 0)*/
#define PCI_CSR_MWI_EN          (1 << 4)        /* Enable Memory Write and    */
                                                /* Invalidate (must be 0)     */
#define PCI_CSR_SC              (1 << 3)        /* Respond to Special Cycles  */
                                                /* (must be 0)                */
#define PCI_CSR_BM              (1 << 2)        /* Master Enable              */
#define PCI_CSR_MS              (1 << 1)        /* Target Memory Enable       */
#define PCI_CSR_IOS             (1)             /* Target I/O Enable          */

/* PCI Slave Image Control for Registers 0, 1,2, and 3 */

#define LSI_CTL_MASK           0x3f380efc      /* Mask bits */
#define LSI_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */
#define LSI_CTL_WP             (1 << 30)       /* Enable Posted Writes       */
#define LSI_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */
#define LSI_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */
#define LSI_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */
#define LSI_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */
#define LSI_CTL_A16            (0 << 16)       /* VME Address Space A16      */
#define LSI_CTL_A24            (1 << 16)       /* VME Address Space A24      */
#define LSI_CTL_A32            (2 << 16)       /* VME Address Space A32      */
#define LSI_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */
#define LSI_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */
#define LSI_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */
#define LSI_CTL_PGM            (1 << 14)       /* Program AM Code            */
#define LSI_CTL_DATA           (0 << 14)       /* Data AM Code               */
#define LSI_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */
#define LSI_CTL_USR            (0 << 12)       /* User AM Code               */
#define LSI_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */
#define LSI_CTL_SINGLE         (0 << 8)        /* User AM Code               */
#define LSI_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */
#define LSI_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */
#define LSI_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Slave Image Base Address Register 0 */

#define LSI0_BS_MASK    0x00000fff

/* PCI Slave Image Bound Address Register 0 */

#define LSI0_BD_MASK    0x00000fff

/* PCI Slave Image Translation Offset Register 0 */

#define LSI0_TO_MASK    0x00000fff

/* PCI Slave Image Base Address Register 1 */

#define LSI1_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 1 */

#define LSI1_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 1 */

#define LSI1_TO_MASK    0x0000ffff

/* PCI Slave Image Base Address Register 2 */

#define LSI2_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 2 */

#define LSI2_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 2 */

#define LSI2_TO_MASK    0x0000ffff

/* PCI Slave Image Base Address Register 3 */

#define LSI3_BS_MASK    0x0000ffff

/* PCI Slave Image Bound Address Register 3 */

#define LSI3_BD_MASK    0x0000ffff

/* PCI Slave Image Translation Offset Register 3 */

#define LSI3_TO_MASK    0x0000ffff

/* PCI Special Cycle Control Register */

#define SCYC_CTL_MASK   	(3 << 0)
#define SCYC_CTL_DISABLE        (0)             /* Disable Special Cycle Gen  */
#define SCYC_CTL_RMW            (1)             /* RMW Special Cycle          */
#define SCYC_CTL_ADO            (2)             /* ADO Special Cycle          */

/* PCI Special Cycle Address Register */

#define SCYC_ADDR_MASK  0xfffffffc

/* PCI Miscellaneous Register */

#define LMISC_CRT_INFINITE      (0 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_128_USEC      (1 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_256_USEC      (2 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_512_USEC      (3 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_1024_USEC     (4 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_2048_USEC     (5 << 28)       /* Coupled Request Timeout */
#define LMISC_CRT_4096_USEC     (6 << 28)       /* Coupled Request Timeout */

#define LMISC_CWT_DISABLE       (0 << 24)       /* Coupled Window Timeout     */
                                /* Immediate Release after first transaction  */
#define LMISC_CWT_16_CLKS       (1 << 24)       /* Coupled Window Timeout     */
#define LMISC_CWT_32_CLKS       (2 << 24)       /* Coupled Window Timeout     */
#define LMISC_CWT_64_CLKS       (3 << 24)       /* Coupled Window Timeout     */
#define LMISC_CWT_128_CLKS      (4 << 24)       /* Coupled Window Timeout     */
#define LMISC_CWT_256_CLKS      (5 << 24)       /* Coupled Window Timeout     */
#define LMISC_CWT_512_CLKS      (6 << 24)       /* Coupled Window Timeout     */

/*
 * Special PCI Slave Image
 * - provides access to all of A16 and most of A24 VME Space
 */
#define SLSI_EN                 (1 << 31)       /* Enable PCI Slave Image     */
#define SLSI_WP                 (1 << 30)       /* Enable Posted Writes       */
#define SLSI_D16                (1 << 20)       /* Max VME Data Width = 16    */
#define SLSI_D32                (2 << 20)       /* Max VME Data Width = 32    */
#define SLSI_PGM                (1 << 12)       /* Program AM Code            */
#define SLSI_DATA               (0 << 12)       /* Data AM Code               */
#define SLSI_SUP                (1 << 8)        /* Supervisor AM Code         */
#define SLSI_USR                (0 << 8)        /* User AM Code               */
#define SLSI_PCI_MEM            (0 << 0)        /* PCI Memory Space           */
#define SLSI_PCI_IO             (1 << 0)        /* PCI I/O Space              */
#define SLSI_PCI_CONFIG         (2 << 0)        /* PCI Type 1 Config Space    */

/* PCI Command Error Log Register */

#define L_CMDERR_LOG            (0xf << 28)     /* Command Error Log          */
#define L_CMDERR_MASK           0x078fffff      /* Reserved bits */
#define L_CMDERR_M_ERR          (1 << 27)       /* Multiple Error Occurred    */
#define L_CMDERR_L_STAT         (1 << 23)       /* Logs are valid and halted  */