universe.h

VxWorks下 Mv2100的BSP源码

/* universe.h - VMEbus Interface Controller */

/* Copyright, 1996-1998 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01m,12jun02,kab  SPR 74987: cplusplus protection
01l,20apr99,rhk  change to support UNIVERSE in non-autoconfig. mode.
01k,24feb99,rhk  changed the macro UNIVERSE_ADRS.
01j,07aug98,tb   Added VMEbus DMA support
01i,14apr98,ms_  merged Motorola mv2700 support
01h,11feb98,tb   Added TAS which uses VMEbus RMW
01g,17dec97,tb   Added Universe II support; added #defines
01f,31oct97,mas  fixed VINT_MAP1* defs, added VINT_MAP0* defs. (SPR 9438).
01e,09jul97,mas  changed LVL0 to UNIVERSE_VOWN_INT; changed LINT_STAT_INT_MASK
		 from 0xd7ff to 0xf7ff; added defs for UNIVERSE_RESERVED_INT,
		 INT_LEVEL_MAP, UNIV_NUM_INT (SPR 8896).
01d,11jun97,mas  removed unused typedefs UNIV_BUS_ADRS, UNIVERSE_REG_TYPE and
		 UNIVERSE_CNFG_HDR.
01c,18feb97,mas  changed VINT...SW_IACK to VINT...SW_INT per MR #39; changed
		 UNIVERSE_VME_IACK_INT to UNIVERSE_VME_SW_INT (SPR 7811).
01b,02jan97,dat  documentation
01a,10jul96,rhk  written.
*/

#ifndef INCuniverseh
#define INCuniverseh

#ifdef __cplusplus
    extern "C" {
#endif

/*
This file contains constants for the Universe PCI-VME interface chip.
The macro UNIVERSE_BASE_ADRS must be defined when including this header.

The registers are listed in ascending (numerical) order; the definitions
for each register are started with a header eg.

NOTE: All XXXX_MASK defines with the comment "Reserved bits" are 
actually incorrect (inverted).  A correct bit mask should have 1's set
for the fields that are of interest, not unused or reserved bits.  
Unfortunately, this code was inherited by MCG and not cleaned up for the
initial release.
*/

#ifdef  _ASMLANGUAGE
# define CASTINT
#else
# define CASTINT (unsigned int *)

/* Structure used to map Universe interrupts to priorities and vectors */

typedef struct int_level_map
{
    int  bitMask;	/* single bit set at associated Universe intr */
    int  vector;	/* vector associated with intr (-1 = query Universe) */
    int  intMask;	/* int enable mask for this level */
} INT_LEVEL_MAP;

#endif  /* _ASMLANGUAGE */

/* Type of PCI to VME bridge device */

#define UNIVERSE_I    1
#define UNIVERSE_II   2

/*
 * Number of interrupts to map in Universe 
 *
 * 32 total bits of which 23 are valid and 9 are reserved (not used),
 * one bit per interrupt.
 */

#define UNIV_NUM_INT	23

/*
 * on-board access, register definitions
 * these registers MUST BE WRITTEN 4-BYTE WRITES ONLY
 * they can be read as byte, two-bytes or 4-bytes.
 */

#ifndef UNIV_ADRS   /* to permit alternative board addressing */
#  if defined(INCLUDE_PCI_AUTOCONF)
#    define UNIV_ADRS(reg)   (CASTINT (univBaseAdrs + reg )) 
#  else
#    define UNIV_ADRS(reg)  (CASTINT (UNIVERSE_BASE_ADRS + reg ))
#  endif
#endif  /* UNIV_ADRS */

/* VME interrupt level definitions */

#define	UNIVERSE_VOWN_INT	0x0001
#define LVL1			0x0002
#define LVL2			0x0004
#define LVL3			0x0008
#define LVL4			0x0010
#define LVL5			0x0020
#define LVL6			0x0040
#define LVL7			0x0080

/* additional VME interrupts supported by the UNIVERSE chip */

#define UNIVERSE_DMA_INT	 0x00000100 /* DMA interrupt bit */
#define UNIVERSE_LERR_INT	 0x00000200 /* PCI bus err interrupt bit */
#define UNIVERSE_VERR_INT	 0x00000400 /* VMEbus err interrupt bit */
#define	UNIVERSE_RESERVED_INT	 0x00000800 /* reserved [DO NOT USE] */
#define UNIVERSE_VME_SW_IACK_INT 0x00001000 /* VME SW IACK interrupt bit */
#define UNIVERSE_PCI_SW_INT	 0x00002000 /* SW interrupt bit */
#define UNIVERSE_SYSFAIL_INT	 0x00004000 /* SYSFAIL interrupt bit */
#define UNIVERSE_ACFAIL_INT	 0x00008000 /* ACFAIL interrupt bit */
#define UNIVERSE_MBOX0_INT	 0x00010000 /* Mailbox 0 interrupt bit */
#define UNIVERSE_MBOX1_INT       0x00020000 /* Mailbox 1 interrupt bit */
#define UNIVERSE_MBOX2_INT       0x00040000 /* Mailbox 2 interrupt bit */
#define UNIVERSE_MBOX3_INT       0x00080000 /* Mailbox 3 interrupt bit */
#define UNIVERSE_LM0_INT	 0x00100000 /* location monitor 0 intr bit */
#define UNIVERSE_LM1_INT         0x00200000 /* location monitor 1 intr bit */
#define UNIVERSE_LM2_INT         0x00400000 /* location monitor 2 intr bit */
#define UNIVERSE_LM3_INT         0x00800000 /* location monitor 3 intr bit */

#define UNIVERSE_INT_MASK	 0x00fff700  /* mask for the interrupts
						defined above */

#define UNIVERSE_CNFG_OFFSET    0x100   /* offset VME specific part */

/* WRITES MUST BE 4-BYTE WRITES ONLY */

/*
 * Device ID - Newbridge allocated device ident    0x00    31-16
 * Vendor ID - PCI SIG allocated vendor identifier 0x00    15-00
 */

#define UNIVERSE_PCI_ID         UNIV_ADRS(0x00)

/* PCI Configuration Space Control and Status Reg  0x00    31-00 */

#define UNIVERSE_PCI_CSR        UNIV_ADRS(0x04)

/*
 * PCI Configuration Class Register
 * PCI Base Class Code - "PCI bridge device"       0x10    31-24
 * PCI Sub Class Code - "other bridge device"      0x10    23-16
 * PCI Programming Interface - (Not Applicable)    0x10    15-08
 * Revision ID                                     0x10    07-00
 */

#define UNIVERSE_PCI_CLASS      UNIV_ADRS(0x08)

/* PCI Configuration Miscellaneous 0 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC0      UNIV_ADRS(0x0c)

/*
 * PCI Base Address Register                       0x08    31-16
 * PCI Bus Address Space Register                  0x08    15-00
 */

#define UNIVERSE_PCI_BS         UNIV_ADRS(0x10)

/* PCI Configuration Miscellaneous 1 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC1      UNIV_ADRS(0x3c)

/* PCI Slave Image 0 Control Register              0x100   31-00 */

#define UNIVERSE_LSI0_CTL       UNIV_ADRS(0x100)

/*
 * PCI Slave Image 0 Base Address Register         0x104   31-12
 * Universe Reserved                               0x104   11-00
 */

#define UNIVERSE_LSI0_BS        UNIV_ADRS(0x104)

/*
 * PCI Slave Image 0 Bound Address Register        0x108   31-12
 * Universe Reserved                               0x108   11-00
 */

#define UNIVERSE_LSI0_BD        UNIV_ADRS(0x108)

/*
 * PCI Slave Image 0 Translation Offset            0x10C   31-12
 * Universe Reserved                               0x10C   11-00
 */

#define UNIVERSE_LSI0_TO        UNIV_ADRS(0x10c)

/* PCI Slave Image 1 Control Register              0x114   31-00 */

#define UNIVERSE_LSI1_CTL       UNIV_ADRS(0x114)

/*
 * PCI Slave Image 1 Base Address Register         0x118   31-12
 * Universe Reserved                               0x118   11-00
 */

#define UNIVERSE_LSI1_BS        UNIV_ADRS(0x118)

/*
 * PCI Slave Image 1 Bound Address Register        0x11C   31-12
 * Universe Reserved                               0x11C   11-00
 */

#define UNIVERSE_LSI1_BD        UNIV_ADRS(0x11C)

/*
 * PCI Slave Image 1 Translation Offset            0x120   31-12
 * Universe Reserved                               0x120   11-00
 */

#define UNIVERSE_LSI1_TO        UNIV_ADRS(0x120)

/* PCI Slave Image 2 Control Register              0x128   31-00 */

#define UNIVERSE_LSI2_CTL       UNIV_ADRS(0x128)

/*
 * PCI Slave Image 2 Base Address Register         0x12C   31-12
 * Universe Reserved                               0x12C   11-00
 */

#define UNIVERSE_LSI2_BS        UNIV_ADRS(0x12C)

/*
 * PCI Slave Image 2 Bound Address Register        0x130   31-12
 * Universe Reserved                               0x130   11-00
 */

#define UNIVERSE_LSI2_BD        UNIV_ADRS(0x130)

/*
 * PCI Slave Image 2 Translation Offset            0x134   31-12
 * Universe Reserved                               0x134   11-00
 */

#define UNIVERSE_LSI2_TO        UNIV_ADRS(0x134)

/* PCI Slave Image 3 Control Register              0x13C   31-00 */

#define UNIVERSE_LSI3_CTL       UNIV_ADRS(0x13C)

/*
 * PCI Slave Image 3 Base Address Register         0x140   31-12
 * Universe Reserved                               0x140   11-00
 */

#define UNIVERSE_LSI3_BS        UNIV_ADRS(0x140)

/*
 * PCI Slave Image 3 Bound Address Register        0x144   31-12
 * Universe Reserved                               0x144   11-00
 */

#define UNIVERSE_LSI3_BD        UNIV_ADRS(0x144)

/*
 * PCI Slave Image 3 Translation Offset            0x148   31-12
 * Universe Reserved                               0x148   11-00
 */

#define UNIVERSE_LSI3_TO        UNIV_ADRS(0x148)

/*
 * Universe Reserved                               0x170   31-02
 * Special Cycle                                   0x170   01-00
 */

#define UNIVERSE_SCYC_CTL       UNIV_ADRS(0x170)

/*
 * Address for Special Cycle                       0x174   31-02
 * Universe Reserved                               0x174   01-00