config.h

VxWorks下 Mv2100的BSP源码

 * the following fixed sizes: 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB,
 * 16 MB, 32 MB, 64 MB, 128 MB or 256 MB each.  Because there are only 4 BATs
 * for data address translation, a maximum of 4 x 256 MB = 1 GB can be
 * mapped this way.
 *
 * Memory usage by TLBs is costly.  For each 128 MB of memory to be mapped,
 * 1 MB of memory is used by TLBs.  A TLB array for 1 GB would require 8 MB!
 */

/* VME Master access windows, set size to 0 to disable a window */

#define	VME_A32_MSTR_BUS	0x08000000	/* Base VME address */
#define VME_A32_MSTR_SIZE	0x08000000
 
/* VME A24 master window, (16MB) */

#define	VME_A24_MSTR_BUS	0x00000000	/* Base VME address */
#define VME_A24_MSTR_SIZE	0x01000000	/* 0 to 16MB, mult of 64K */

/* VME A16 Master window (64KB) */

#define VME_A16_MSTR_SIZE	0x00010000	/* either 0 or 64KB, only */

/* Setup VME slave windows, set size to 0 to disable a window */

/*
 * VME A32 slave window, default is to map all local memory to VMEbus.
 * The window size is set to LOCAL_MEM_SIZE.  This will reduce the window
 * size if LOCAL_MEM_SIZE does not reflect the actual amount of memory.
 * Hence, if all of physical memory is to be addressed in the A32 window,
 * the actual board memory size should be set in LOCAL_MEM_SIZE.
 */

#define VME_A32_SLV_LOCAL    LOCAL_MEM_LOCAL_ADRS
#define VME_A32_SLV_BUS	     VME_A32_MSTR_BUS
#define VME_A32_SLV_SIZE     (((ULONG)sysPhysMemTop()) - (LOCAL_MEM_LOCAL_ADRS))

/* VME A24 slave window, default is to not enable */

#define VME_A24_SLV_LOCAL       LOCAL_MEM_LOCAL_ADRS
#define VME_A24_SLV_BUS         VME_A24_MSTR_BUS
#ifdef A24_SLV_WINDOW
#define VME_A24_SLV_SIZE        VME_A24_MSTR_SIZE	/* set to max, 16MB */
#else
#define VME_A24_SLV_SIZE        0x0     /* 0, window is disabled */
#endif

/* VME A16 slave window, no default support */


#ifdef	INCLUDE_VME_DMA
/* Default DMA operating parameters used by sysVmeDmaInit() */

/*
 * VMEbus data transfer type
 * - a combination of VMEbus Max. Datawidth (VDM) and
 *   VMEbus Cycle Type (VCT).
 *
 *	choices:
 *		(DCTL_VDW_8  | DCTL_VCT_SINGLE)
 *		(DCTL_VDW_16 | DCTL_VCT_SINGLE)
 *		(DCTL_VDW_32 | DCTL_VCT_SINGLE)
 *		(DCTL_VDW_64 | DCTL_VCT_SINGLE)
 *		(DCTL_VDW_32 | DCTL_VCT_BLK)	** BLT  **
 *		(DCTL_VDW_64 | DCTL_VCT_BLK)	** MBLT **
 */

#define	VME_DMA_XFER_TYPE	(DCTL_VDW_32 | DCTL_VCT_SINGLE)

/*
 * VMEbus Address Space type
 *	choices:
 *		DCTL_VAS_A16
 *		DCTL_VAS_A24
 *		DCTL_VAS_A32
 */

#define	VME_DMA_ADDR_SPACE	DCTL_VAS_A32

/*
 * Program/Data Address Modifier (AM) Code
 *	choices:
 *		DCTL_PGM_DATA
 *		DCTL_PGM_PRGM
 */

#define	VME_DMA_DATA_TYPE	DCTL_PGM_DATA

/*
 * Supervisor/User Address Modifier (AM) Code
 *	choices:
 *		DCTL_SUPER_USER
 *		DCTL_SUPER_SUP
 */

#define	VME_DMA_USER_TYPE	DCTL_SUPER_SUP

/*
 * VMEbus Aligned DMA Transfer Count (in bytes)
 * - Max. data transferred before giving up the VMEbus
 *	choices:
 *		DGCS_VON_DONE
 *		DGCS_VON_256
 *		DGCS_VON_512
 *		DGCS_VON_1024
 *		DGCS_VON_2048
 *		DGCS_VON_4096
 *		DGCS_VON_8192
 *		DGCS_VON_16384
 */

#define	VME_DMA_MAX_BURST		DGCS_VON_DONE

/*
 * Minimum period the DMA is off the VMEbus between tenures (in microseconds)
 *	choices:
 *		DGCS_VOFF_0
 *		DGCS_VOFF_16
 *		DGCS_VOFF_32
 *		DGCS_VOFF_64
 *		DGCS_VOFF_128
 *		DGCS_VOFF_256
 *		DGCS_VOFF_512
 *		DGCS_VOFF_1024
 */

#define	VME_DMA_MIN_TIME_OFF_BUS	DGCS_VOFF_0

#endif	/* INCLUDE_VME_DMA */

/*
 * These defines are used to initialize the External Source
 * Vector/Priority registers in the EPIC.  The following can
 * be defined: interrupt sensitivity, polarity and interrupt priority.
 *
 * Note: by default a 0 into the sense bit(22) will setup for level
 * sensitive, and a 0 into the polarity bit(23) will setup for low
 * polarity.
 *
 * At initialization all external interrupt sources are disabled.
 *
 * All currently unused interrupt sources are set to a priority of
 * 0, which will not allow them to be enabled.  If any one of these
 * levels is to be used, the priority value must be changed here.
 */
 
#define INIT_SER_SRC0           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_SER_SRC1           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL14 )  /* primary ethernet */
 
#define INIT_SER_SRC2           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL9 )  /* PC-MIP Type 1 Slot 1 */
 
#define INIT_SER_SRC3           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL8 )  /* PC-MIP Type 1 Slot 2 */

#define INIT_SER_SRC4           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL7 )  /* PC-MIP Type 2 Slot 1 */
 
#define INIT_SER_SRC5           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL6 )  /* PC-MIP Type 2 Slot 2 */
 
#define INIT_SER_SRC6           ( INT_MASK_BIT |\
                                  EDGE_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )  /* Not used */
 
#define INIT_SER_SRC7           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTA, 
                                                       U2.LINT0 */
 
#define INIT_SER_SRC8           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTB, 
                                                       U2.LINT1 */

#define INIT_SER_SRC9           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTC, 
                                                       U2.LINT2 */

#define INIT_SER_SRC10          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL13 )  /* PCI expansion INTD, 
                                                       U2.LINT3 */

#define INIT_SER_SRC11          ( INT_MASK_BIT |\
                                  EDGE_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */
 
# define INIT_SER_SRC12         ( INT_MASK_BIT |\
                                  EDGE_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_SER_SRC13          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  HIGH_POLARITY |\
                                  PRIORITY_LVL5 )   /* 16550 UART (COM1) */
 
#define INIT_SER_SRC14          ( INT_MASK_BIT |\
                                  EDGE_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL4 )  /* abort switch */
 
#define INIT_SER_SRC15          ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL3 )   /* RTC */

/* External interrupt sources */

#define INIT_EXT_SRC0           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */

#define INIT_EXT_SRC1           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */

#define INIT_EXT_SRC2           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */

#define INIT_EXT_SRC3           ( INT_MASK_BIT |\
                                  LEVEL_SENSE |\
                                  LOW_POLARITY |\
                                  PRIORITY_LVL0 )   /* not used */

/* Initial timer values */

#define INIT_TMR_SRC0           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* AUX Clock */

#define INIT_TMR_SRC1           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_TMR_SRC2           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_TMR_SRC3           ( TIMER_INHIBIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial DMA interrupt values */

#define INIT_DMA_SRC0           ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

#define INIT_DMA_SRC1           ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial I2C interrupt value */

#define INIT_I2C_SRC            ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/* Initial message unit interrupt value */

#define INIT_MSGUNIT_SRC        ( INT_MASK_BIT |\
                                  PRIORITY_LVL0 )   /* off */

/*
 * The following NETIF... macros augment the NETIF table defined in
 * "usrNetwork.c".  The NETIF table entry defined here will be compiled
 * at the beginning of the table and thus be found first prior to the
 * "dcattach()" call.  Instead of calling "dcattach()" directly, the
 * function "sysDynDcAttach()" is called which in turn calls "dcattach()"
 * with a DYNAMICALLY determined CPU based I/O address, rather than
 * the statically compiled address IO_ADRS_DC.
 */

#if defined(INCLUDE_PCI_AUTOCONF) && \
    defined(INCLUDE_NETWORK) && !defined(INCLUDE_END)

#define NETIF_USR_DECL  IMPORT STATUS sysDynDcAttach(); \
                        IMPORT STATUS dcattach();
#define NETIF_USR_ENTRIES \
    { "dc", sysDynDcAttach, (char*)IO_ADRS_DC, INT_VEC_DC, INT_LVL_DC, \
      DC_POOL_ADRS, DC_POOL_SIZE, DC_DATA_WIDTH, DC_RAM_PCI_ADRS, \
      DC_MODE },

#endif /* defined(INCLUDE_PCI_AUTOCONF, INCLUDE_NETWORK, !INCLUDE_END) */

/* BSP-specific includes */

#include "mv2100.h"

#ifdef __cplusplus
}
#endif

#endif	/* INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif