target.nr

VxWorks下 Mv2100的BSP源码

The slave (incoming VME) window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave
Address Space	Size	VME Base Address	Local Base Address
_
A16 (none)
A24 (none)
A32	128MB	0x08000000	0x00000000
A32 (Mailbox)	4KB	0xFB000000	(none)
.TE

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address maps created from the CPU point of view.  Tornado-compatible
mapping deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x80000000 - LOCAL_MEM_SIZE)	[Not used]
0x80000000	8MB	PCI ISA I/O space
0x80800000	8MB	Direct PCI Config. Space
0x81000000	(1GB - 32MG)	PCI I/O space
0xC0000000	16MB	PCI ISA MEM space
0xC1000000	(1GB - 32MG)	PCI MEM space
0xC1000000	128MB	Dynamic PCI Mem space
0xEFE00000	1MB	Kahlua registers
0xFF000000	16MB	ROM space
.TE

.SS "VME Access in the Pseudo-PReP Memory Model" 1

The pseudo-PReP memory model does not offer much address space for mapping
VME master windows.  Only 128MB of A32 space is available.  The 128MB window
can be mapped anywhere in VME A32 space by setting the macro VME_A32_MSTR_BUS
in config.h.  The full A16 and A24 master window address spaces are mapped into
the system.

The master (outgoing VME) window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	Size	Local Base Address	VME Base Address
_
A16	64KB	0xEFFF0000	0xXXXX0000
A24	16MB	0xE0000000	0xXX000000
A32	128MB	0xD8000000	0x08000000
A32 (Mailbox)	4KB	0xF0000000	0x40000000
.TE

The slave (incoming VME) window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave
Address Space	SIZE	VME Base Address	Local Base Address
_
A16 (none)
A24 (none)
A32	128MB	0x00000000	0x00000000
A32 (Mailbox)	4KB	0x40000000	0x00001000 (UNIV II LM Reg)
.TE

.SS "PCI Access in the Pseudo-PReP Memory Model" 1

The default pseudo-PReP mapping from the PCI bus point of view is:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x00000000	16MB (max)	PCI ISA MEM space
0x01000000	(1GB - 32MB)	PCI MEM space
0x01000000	128MB (max)	Dynamic PCI MEM space
0x18000000	16MB (std)	VME A32 master space
0x20000000	16MB (max)	VME A24 master space
0x2FE00000	1MB (fixed)	Kahlua registers
0x2FFF0000	64KB (max)	VME A16 master space
0x80000000	16MB (min)	DRAM space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	64KB	PCI ISA I/O space
0x00010000	8MB-64KB	Reserved
0x00800000	1GB-16MB	PCI I/O space
0x3F800000	3GB+8MB	Reserved
.TE


Remember to set LOCAL_MEM_SIZE to the actual amount of DRAM on the board if
auto-sizing is not selected.  Failure to do so can cause unpredictable results
for A32 masters and slaves.

In config.h, \f3#define\f1 the VME window variables.

In sysLib.c, edit the sysPhysMemDesc[] page table to modify the A32 VME
window if you modify the sysBatDesc[] BAT register table.  The BAT registers
allow mapping of up to 1GB of data address space.  Although the BAT registers
are not supported in the current cache management strategy, you can use them
for non-cacheable, data-only address regions, like the VME A32 address space.

.SS "Shared Memory"
On all boards, shared memory across the backplane can also be used as a
network interface.  The name of the shared memory is `sm'.

Shared memory network communications requires a signaling method and a method
of mutually exclusive memory resource access.  Signalling can be done using
software polling or interrupts.  By default, mailbox interrupts are used and
SM_INT_TYPE is set to SM_INT_MAILBOX_1.  To use polling, \f3#define\f1
SM_INT_TYPE as SM_INT_NONE.

There are master and slave windows into VME address space to access the VME
mailbox registers so that each CPU can send and receive shared memory interrupts
using single-byte mailboxes.
The windows map a 4KB region in A32 space at address 0xFB000000 + (0x1000 *
CPU #) into the Universe chip registers.  This configuration allows one
processor to generate a SIG1 interrupt in another processor by accessing the
other processor's mailbox register and setting the SIG1 bit.  Each CPU has a
master window covering the A32 addresses 0xFB000000 through 0xFB00ffff
representing CPU numbers 0 through 15.  Each CPU's slave window maps the
appropriate address for that CPU to the Universe chip's register set.

Shared memory resource mutual exclusion (spin lock) is implemented using
test-and-set (TAS) and clear operations on byte-sized semaphores.
If the \f3#define\f1 SM_TAS_TYPE is set to SM_TAS_SOFT, only a software TAS
routine is used.  Software TAS is usually good enough for shared memory
networking; however, VxMP requires the use of hardware TAS.  Enable hardware
TAS by setting SM_TAS_TYPE to SM_TAS_HARD.  Hardware TAS and clear operations
are performed by the sysBusTas() and sysBusTasClear() routines, respectively,
and invoke pseudo-atomic operations.

True atomic operations are those which cannot be preempted at the hardware
level and appear on a bus as a single-cycle instruction.  Pseudo-atomic
operations are composed of multiple instruction cycles executed on a
bus that is locked (owned) by the processor executing the instructions.

The routine sysBusTas() performs pseudo-atomic TAS operations by disabling
interrupts (to prevent deadlocks) and locking ownership of the VMEbus.  This
routine waits up to 10 microseconds to lock the bus.  If bus ownership has not
been achieved at the end of this period, the routine returns FALSE, the same as
it would if the semaphore had already been set.

VMEbus ownership is necessary for a couple of reasons.  First, there is no
hardware support to propagate PowerPC atomic TAS instructions to the
Universe chip.  Second, these boards have no support for propagating
true atomic VME RMW cycles to local processor memory.

To ensure proper clearing of the semaphore, use the sysBusTasClear().  This
routine also disables interrupts and locks the VMEbus while accessing the
semaphore.  It waits up to 10 microseconds to gain bus ownership.  But, even if
the bus is not owned after this period, the routine attempts to clear the
semaphore.

If one board uses software TAS, then \f2all\f1 boards on a shared
memory backplane must use it.

When hardware TAS is enabled, special consideration must be given to the
overall system design and board locations in the VME card rack.  If all VME
boards on a backplane use the special hardware TAS methods utilized in this BSP,
there should be no problems.  If boards with differing TAS/RMW capabilities are
used together, then either the first (master) board, which hosts the shared
memory, must use the hardware TAS method utilized in this BSP, or the shared
memory must reside on a separate VME global memory board.

As an example of a hardware TAS system that cannot work, consider using a
Motorola MVME162 as the master board and an MVME2100 as a slave.  The
mv162 BSP assumes that support exists for atomic TAS/RMW cycles on to and off of
all boards in the system.  Furthermore, the local 68040 CPU can access and alter
its memory \f2between\f1 VMEbus cycles.  Therefore, this system configuration
does not work because there is no way to ensure atomic access to a semaphore by
the MVME2100 board.

.SS "Interrupts"
The Embedded Programmable Interrupt Controller (EPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers can be programmed with a relative
priority from 15, the highest, to 0, the lowest.  A priority of zero
effectively disables the interrupt.  All of the 16 control registers have
been hardwired to a particular interrupt source.  The EPIC interrupt
controller will operate in the serial interrupt mode.

The external interrupt vector numbers and priority assignments are:


.TS C
center;
lf3 lf3 lf3
l l l .
.ne 14
.sp .5
Vector#	EPIC Priority	Interrupt Source
_
   0	0	Not Used
   1	14	DEC21143 Ethernet Controller
   2	9	PMC/PC-MIP Type I Slot 0
   3	8	PC-MIP Type I Slot 1
   4	7	PC-MIP Type II Slot 0
   5	6	PC-MIP Type II Slot 1
   6	0	Not Used
   7	13	PCI Expansion Interrupt A/Universe II (LINT0)
   8	13	PCI Expansion Interrupt B/Universe II (LINT1)
   9	13	PCI Expansion Interrupt C/Universe II (LINT2)
   a	13	PCI Expansion Interrupt D/Universe II (LINT3)
   b	0	Not Used
   c	0	Not Used
   d	5	16550 UART
   e	4	Front panel Abort Switch
   f	3	RTC/IRQ
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the EPIC and, therefore, have pre-assigned system vector numbers
and interrupt levels.  The user enables one or more PCI interrupts and connects
vectored ISRs to the system by following these steps:

.IP "1)"
Identify the PCI interrupt letter(s) as required by the  application. Based on 
this, identify the associated system interrupt level from the following tables:

            Primary PCI Bus
            ----------------
            A = PMC_INT_LVL1
            B = PMC_INT_LVL2
            C = PMC_INT_LVL3
            D = PMC_INT_LVL4

            Secondary PCI Bus
            -----------------
            A = PMC_INT_LVL4
            B = PMC_INT_LVL3
            C = PMC_INT_LVL2
            D = PMC_INT_LVL1

.IP "2)"
Define the vector for each PCI interrupt as follows:
INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4, as determined above.
.IP "3)"
In the application code, perform intConnect() for
each vector and its associated ISR.
.IP "4)"
Perform sysIntEnable() for each identified system interrupt level.
.IP "5)"
When the application has finished, perform sysIntDisable() for each identified 
level.

.SS "PCI Auto-Configuration"
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI
auto-configuration library. When INCLUDE_AUTOCONF is defined, the BSP will
automatically locate and configure installed PCI devices. When
INCLUDE_AUTOCONF is not defined, add-in PCI devices will not be located or
configured.

If PCI auto-configuration is selected, the auto-cofiguration library will be
called from sysHwInit to discover and configure the installed PCI devices and
bridges. Device configuration includes the following PCI information:

.IP "Base Address Registers (BARs)"
Space in the address map is dynamically allocated to each valid BAR detected.
Allocation pools are maintained for the following PCI address spaces:


16-Bit PCI I/O
.br
32-Bit PCI I/O
.br
PCI Memory I/O (non-prefetchable memory)
.br
PCI Memory (pre-fetchable)

.IP "Interrupt Routing"
The correct interrupt vector number is placed in the intLine register of the
device's PCI header. To connect to the devices's interrupt, simply call
intConnect with the value read from intLine.

.IP "PCI Header Completion"
The PCI auto-configuration library fills in the remainder of the PCI header as
follows:
.sp
Cache Line Size  = _CACHE_ALIGN_SIZE/8
.sp
Latency Timer    = PCI_LAT_TIMER
.sp
Command Register = I/O enabled, Memory enabled and Bus Master enabled.

.IP "PCI-to-PCI Bridge Configuration"
PCI-to-PCI bridges encountered during PCI auto-configuration will be configured
as necessary and devices detected behind the bridge will be configured as
described above. Bridge configuration consists of the following:

Primary Bus Number, Secondary Bus Number and Subordinate Bus Number are
filled in according to the bridge's position in the system.
.sp
I/O Base and Limit registers are configured as required to forward PCI
transactions to PCI devices detected and configured beyond the bridge.
.sp
Memory Base and Memory Limit regsiters are configured as required to forward
PCI transactions to PCI devices detected and configured beyond the bridge.
.sp
Prefetchable Memory Base and Prefetchable Memory Limit are configured as
required to forward PCI transactions to PCI devices detected and confured
beyond the bridge.
.sp
Command Register = I/O enabled, Memory enabled and Bus Master enabled.
.sp
Cache Line Size         = _CACHE_ALIGN_SIZE/8
.sp
Primary Latency Timer   = PCI_LAT_TIMER
.sp
Secondary Latency Timer = PCI_LAT_TIMER

.SS "Serial Configuration"
The single serial port on the MVME2100 board family is implemented as a SCC
16550 UART.  The RJ-45 jack is placed on the front panel of the board
and is configured as a DTE connection.

By default, the serial port is configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option.

.SS "SCSI Configuration"
SCSI is not available on the MVME2100 board family.

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX compatible.
The MVME2100 boards have an RJ45 jack on their front panel for connection
to this facility.

The Ethernet driver automatically senses and configures the port as 10baseT or
100baseTX.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21143 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM.