target.nr

VxWorks下 Mv2100的BSP源码

'\" t
.so wrs.an
.\" target.nr - Motorola MVME2100 target-specific documentation
.\"
.\" Copyright 2002 Wind River Systems, Inc.
.\" Copyright 1996-2000 Motorola, Inc. All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01l,21mar02,kab  remove ref to elfToBin (obs in T2.2); 
.\"		     add supported target list.
.\" 01k,27aug01,dgp  change manual pages to reference entries per SPR 23698
.\" 01j,15jun00,dmw  updated following WRS code review.
.\" 01i,08feb00,rhk  added description of power on problem.
.\" 01h,22dec99,rhk  modified instructions for flashing bootroms, added more
.\" 		     information to "ROM Considerations" section.
.\" 01g,25jun99,srr  added documentation for Tornado 1.0.1 support.
.\" 01f,22jun99,srr  removed NETIF support and documented ECC support.
.\" 01e,04jun99,rhk  format changes, changed PCI interrupt priorites to all 
.\" 		     be 13, added errata info about EPIC interrupts, modified
.\" 		     the PCI/VME address ranges.
.\" 01d,13may99,rhk  updates for NETIF, board layout, board jumpers, added
.\" 		     information on PCI autoconfig, general cleanup.
.\" 01c,05apr99,rhk  updated the memory maps, hardware information,
.\"		     interrupt tables, serial configuration, universe info.
.\" 01b,17feb99,srr  added SENS info.
.\" 01a,14dec98,srr  created (from mv2303/target.nr ver 01u.)
.\"
.\"
.TH "mv2100" T "Motorola" "Rev: 25 Jun 99" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MVME2100"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

This BSP encompasses only the MVME2100 board.

The MVME2100 board is a single-board computer based on the PowerPC MPC8240
microprocessor.

    MVME2100

The BAT registers are not supported in the current cache management strategy.

.SS "Boot ROMS"
The MVME2100 boards have two sets of flash EEPROM (FLASH).  Bank A consists
of two 32-pin PLCC sockets which can be populated with up to 1024KB of
FLASH memory.  It resides at address 0xFFF00000 and is restricted to 8 bits
in width.  This memory contains Motorola's PPC1-Bug.
Bank B may be populated with four 512Kx16 FLASH devices to obtain 4MB of 64-bit
wide expansion FLASH memory or four 1Mx16 FLASH devices to obtain 8MB of 64-bit
wide FLASH memory.  The expansion FLASH memory starts at address 0xFF000000.
FLASH is soldered in on the back of the boards.  The VxWorks boot kernel resides
in the soldered FLASH.
See \f2Hardware Details: ROM Considerations\f1 for information about loading and
writing the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 28
.sp .5
Jumper	Function	Description
_
J2	System controller	T{
Install the jumper across pins 2 and 3, if you wish to operate in
"automatic" system controller mode [factory configuration].  Install the
jumper across pins 1 and 2, if the board is not to be the system controller
under any circumstances.  And remove the jumper if the board is to be the
system controller in all cases.
T}
J9	ROM controller	T{
Remove the jumper across pins 1 and 2 to select the socketed FLASH.
Install the jumper from pins 1 and 2 to select the soldered FLASH.
[factory configuration].
T}
J9	User Configurable	T{
The remaining jumpers in the J9 jumper bank have no preset function and
can be configured by users as necessary.
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MVME2100 board are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 7
.sp .5
Feature	Description
_
Processor	T{
MPC8240 (MPC603 based); 66.67 and 83.33MHz bus clock
T}
FLASH	T{
1MB socketed (8-bit wide);
4 or 8MB expansion (64-bit wide)
T}
DRAM	T{
32, 64, 96MB ECC Synchronous DRAM (SDRAM)
T}
Memory Model	T{
Both CHRP and PReP models are supported
T}
NVRAM	T{
8KB (MK48T59Y)
T}
Peripherals	T{
one 16550-compatible async serial debug port;
DEC21143 10/100Base-TX Ethernet interface
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
VME Interface	T{
32-bit address, 32-bit data PCI bus interface;
A32/A24/A16, D32/D16/D08 master and slave;
programmable interrupter and interrupt handler;
full system controller function;
four 32-bit mailbox registers;
four location monitors;
eight semaphores
T}
Miscellaneous	T{
RESET switch
T}
.TE

.SS "Unsupported Features"
The following features of the MVME2100 board are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
RTC	T{
MK48T59/559; only NVRAM portion is used
T}
DMA Channels	T{
2 Independent DMA Channels
T}
I2O Interface	T{
I2O compliant messaging interface
T}
PCI Interface	T{
64-bit data
T}
VME Interface	T{
D64(MBLT); programmable DMA controller with linked list support
T}
Miscellaneous	T{
ABORT switch, 4 status LEDs
T}
.TE

.SS "Feature Interactions"
None known.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP are:

.nf
    `i8250Sio' - Intel 8250 UART driver (debug port)
    `ppcDecTimer' - PowerPC decrementer timer driver (system clock)
    `dec21x40[End].obj' - 10baseT/100baseTX DEC 21x40 Ethernet driver
    `byteNvRam' - byte-oriented generic non-volatile RAM driver
    `kahluaEpic' - Motorola Kahlua EPIC interrupt controller driver
    `pciConfigLib' - PCI configuration library
    `universe' - Tundra Universe II chip VME-to-PCI interface driver
    `sysI2cDrv' - Kahlua I2C interface driver
.fi

.SS "NETIF support"
This BSP supports the END (Enhanced Network Driver) as the only
network interface for Tornado 2.

.SS "ECC support"
This BSP supports ECC memory on the MVME2100.  The default configuration is
for the ECC support to be disabled so the default BSP will run in all
board memory configurations.  To enable ECC support, INCLUDE_ECC must
be changed from undef to define.

.SS "Tornado 1.0.1 SENS/Shared Memory Support"
This BSP supports SENS (Scalable Enhanced Network Stack) only.  There is
a problem with using shared memory booting and Tornado 1.0.1 SENS.  Wind River
has provided a patch for SPR 21838 which has been included in the mv2100
BSP, but additional configuration is required to install it.
This fix must NOT be done on Tornado 2.0!

.LP
To configure the BSP to run with Tornado 1.0.1 SENS so shared memory booting
works, install SENS in the Tornado 1.0.1 build area and make the following
adjustments in the "mv2100" subdirectory and rebuild:

.IP "1)"
From the "mv2100" subdirectory perform: 
.CS
  mv ../all/bootConfig.c ../all/bootConfig.c.orig
  mv ../all/bootInit.c ../all/bootInit.c.orig
  cp ./tornado_1.0.1/bootConfig.c ../all/bootConfig.c
  cp ./tornado_1.0.1/bootInit.c ../all/bootInit.c
.CE

.IP "2)"
From the "mv2100" subdirectory perform: 
.CS
  mv ../../src/config/usrNetwork.c \\
     ../../src/config/usrNetwork.c.orig
  cp ./tornado_1.0.1/usrNetwork.c ../../src/config/usrNetwork.c
.CE

.IP "3)"
Rebuild the bootroms and kernel and reflash the bootroms.

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.
Its slave address on the VMEbus is set by registers in the Universe ASIC.
Local RAM-to-VMEbus mapping is defined in config.h

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size
of DRAM memory available on the board to ensure all memory is available
and VME addressing occurs properly.  The default fixed RAM size is set to 16MB
(see LOCAL_MEM_SIZE in config.h).

The MV2100 supports two memory mappings.  The default for the MV2100 BSP is
the CHRP map, the optional mapping is PReP.  The mappings are selected by
defining or undefinig the macro CHRP_ADRS_MAP, which will determine the
setting of the ADDRESS_MAP bit in the Kahlua Processor Interface Configuration
Register 1.  At power-on the bit is configured by sampling the MAA(0) signal.
The default hardware/software setup is for CHRP.

.SS "CHRP Address Maps"
The following tables describe the CHRP address mappings.  Most of the
address maps are fixed by hardware and the base addresses cannot be modified
by the user.

Table I.    CHRP Map From CPU Point of View.

.TS E
expand;
lf3 lf3 lf3
lf3 lf3 lf3
l l l .
.ne 6
.sp .5
Start	Size	Access to
_
0x00000000	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x40000000 - LOCAL_MEM_SIZE)	Unused DRAM space
0x40000000	1GB	Reserved
0x80000000	0x7CFFFFFF	PCI Memory Space
   0x80000000	0x72000000	VME Space (see Table II )
   0xF2000000	128MB	Dynamic PCI Mem space
   0xFCF00000	1MB	Kahlua registers
0xFD000000	16MB	PCI ISA Memory Space
0xFE000000	64KB	PCI ISA I/O Space
0xFE800000	4MB	PCI I/O Space
0xFEC00000	32MB	Configuration Addr Reg.
0xFEE00000	16MB	Configuration Data Reg.
0xFEF00000	16MB	PCI interrupt Ack.
0xFF000000	8MB	32/64 bit FLASH/ROM
0xFF800000	8MB	8/32/64 bit FLASH/ROM
.TE



Table II.    CHRP CPU to VME Map.

.ne 10
The master (outgoing VME) window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	Size	Local Base Address	VME Base Address
_
A32	128MB	0x80000000	0x08000000
A24	16MB	0xF0000000	0xXX000000
A32 (Mailbox)	4KB	0xF1000000	0xF1000000
A16	64KB	0xF1FF0000	0xXXXX0000
.TE



Table III.   CHRP Map on PCI Bus.

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x00000000	1GB (max)	DRAM space
0x40000000	1GB (fixed)	Reserved
0x80000000	2GB-48MB	PCI MEM space
0x80000000	1.75GB (max)	VME A32 master space
0xF0000000	16MB (std)	VME A24 master space
0xF1000000	64KB (std)	VME mailbox (A32) space	
0xF1FF0000	64KB (std)	VME A16 master space
0xF2000000	128MB (max)	Dynamic PCI Mem space
0xFCF00000	1MB (fixed)	Kahlua registers
0xFD000000	16MB (max)	DRAM space
0xFE000000	16MB (fixed)	Reserved
0xFF000000	8MB (max)	32/64 bit FLASH ROM space
0xFF800000	8MB (max)	8/32/64 bit FLASH ROM space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	64KB	ISA I/O space
0x00010000	8MB-64KB	Reserved
0x00800000	4MB	PCI I/O space
0x00C00000	4GB-12MB	Reserved
.TE



Table IV.    CHRP Map on VMEbus.

.ne 10