mv2100.h

VxWorks下 Mv2100的BSP源码

#endif /* CHRP_ADRS_MAP */
#if (VME_A24_MSTR_SIZE > 0x01000000)
#  error Maximum VME_A24_MSTR_SIZE cannot exceed 16 MB
#endif /* (VME_A24_MSTR_SIZE > 0x01000000) */
#define VAL_LSI2_BS	(VAL_LSI2_BS_VALUE)
#define VAL_LSI2_BD	(VAL_LSI2_BS + VME_A24_MSTR_SIZE)
#define VAL_LSI2_TO	(0xff000000 + VME_A24_MSTR_BUS - VAL_LSI2_BS)
#define VAL_LSI2_CTL	( LSI_CTL_EN     | LSI_CTL_WP  |\
                          LSI_CTL_D64    | LSI_CTL_A24 |\
                          LSI_CTL_DATA   | LSI_CTL_USR |\
                          LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * VME MASTER WINDOW FOR A16 SPACE
 *
 * Universe PCI slave (VME master) window 3
 */

#ifndef CHRP_ADRS_MAP		/* PReP values */

/*
 * Map access to A16 VMEbus - 64K       MAP FOR PReP vxWorks
 * This maps: MPU RANGE:     0xefff0000 - 0xefffffff  
 *        to: PCI RANGE:     0x2fff0000 - 0x2fffffff
 *        to: VME RANGE:     0xffff0000 - 0xffffffff
 */

#  define VME_A16_MSTR_LOCAL	(PCI_MSTR_MEM_LOCAL + 0x2eff0000)
#  define VAL_LSI3_BS_VALUE	(VME_A16_MSTR_LOCAL - PCI_MSTR_MEMIO_LOCAL)
#else				/* CHRP values */

/*
 * Map access to A16 VMEbus - 64K       MAP FOR CHRP map vxWorks
 * This maps: MPU RANGE:     0xf1ff0000 - 0xf1ffffff
 *        to: PCI RANGE:     0xf1ff0000 - 0xf1ffffff
 *        to: VME RANGE:     0xf1ff0000 - 0xf1ffffff
 */

#  define VME_A16_MSTR_LOCAL	(PCI_MSTR_MEM_LOCAL + 0x71ff0000)
#  define VAL_LSI3_BS_VALUE	(VME_A16_MSTR_LOCAL)
#endif /* CHRP_ADRS_MAP */
#if  (VME_A16_MSTR_SIZE > 0x00010000)
#  error Maximum VME_A16_MSTR_SIZE cannot exceed 64 KB
#endif /* (VME_A16_MSTR_SIZE > 0x00010000) */
#define	VME_A16_MSTR_BUS	0x00000000	/* must be 0 */
#define VAL_LSI3_BS		(VAL_LSI3_BS_VALUE)
#define VAL_LSI3_BD		(VAL_LSI3_BS + VME_A16_MSTR_SIZE)
#define VAL_LSI3_TO		(0xffff0000 + VME_A16_MSTR_BUS - VAL_LSI3_BS)
#define VAL_LSI3_CTL		( LSI_CTL_EN     | LSI_CTL_WP  |\
                                  LSI_CTL_D64    | LSI_CTL_A16 |\
                                  LSI_CTL_DATA   | LSI_CTL_USR |\
                                  LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * VME MASTER MEMORY WINDOW LIMITS
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks of the VME bus to work properly.
 */

#ifndef CHRP_ADRS_MAP
#  define VME_MSTR_LO_ADRS      (VME_A32_MSTR_LOCAL)
#  define VME_MSTR_HI_ADRS      (VME_LM_MSTR_LOCAL + VME_LM_MSTR_SIZE)
#else
#  define VME_MSTR_LO_ADRS      (VME_A32_MSTR_LOCAL)
#  define VME_MSTR_HI_ADRS      (VME_A16_MSTR_LOCAL + VME_A16_MSTR_SIZE)
#endif  /* CHRP_ADRS_MAP */

/* 
 * Defines for the VME SLAVE WINDOWS
 *
 * Allows for the decoding of addresses on the VMEbus.
 */

/*
 * VME SLAVE WINDOW FOR A32 SPACE
 *
 * Universe VME slave window 1
 *
 * VME bus A32 window to access the master node's local memory.
 * This VME Slave window is only used by the master node.
 * 
 *                      vxWorks PReP Map
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x80000000 - 0x80000000 + VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 *
 *                      vxWorks CHRP Map
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 */

#define VAL_VSI1_BS	(VME_A32_SLV_BUS)

#if	(SM_OFF_BOARD == TRUE)
#  define VAL_VSI1_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#else
#ifdef	ANY_BRDS_IN_CHASSIS_NOT_RMW
#  define VAL_VSI1_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#else
#  define VAL_VSI1_BD     (VAL_VSI1_BS + SM_MEM_ADRS)
#endif	/* ANY_BRDS_IN_CHASSIS_NOT_RMW */
#endif	/* SM_OFF_BOARD */

#define VAL_VSI1_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI1_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN )

#ifdef A24_SLV_WINDOW
/*
 * VME SLAVE WINDOW FOR A24 SPACE
 *
 * Universe VME slave window 2
 *
 * VME bus A24 window to access the master node's local memory.
 * This VME Slave window is only used by the master node.
 *
 *                      vxWorks PReP Map
 * This maps: VME RANGE:     0x00000000 - (VME_A24_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x80000000 - 0x80000000 + VME_A24_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A24_SLV_SIZE-1
 *
 *                      vxWorks CHRP Map
 * This maps: VME RANGE:     0x00000000 - (VME_A24_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x00000000 - VME_A24_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A24_SLV_SIZE-1
 */

#define VAL_VSI2_BS     (VME_A24_SLV_BUS)
#define VAL_VSI2_BD	(VAL_VSI2_BS + VME_A24_SLV_SIZE)
#define VAL_VSI2_TO	(PCI_SLV_MEM_BUS - VAL_VSI2_BS + VME_A24_SLV_LOCAL)
#define VAL_VSI2_CTL    ( VSI_CTL_EN       | VSI_CTL_PREN    | \
                          VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
                          VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
                          VSI_CTL_VAS_A24  | VSI_CTL_LAS_MEM | \
                          VSI_CTL_LD64EN )
#endif /* A24_SLV_WINDOW */

/*  VSI4 and VSI5 are only applicable to the Universe II */

#define VAL_VSI4_BS	(VAL_VSI1_BS + \
			 SM_MEM_ADRS)
#define VAL_VSI4_BD	(VAL_VSI1_BS + \
			 SM_MEM_ADRS + \
			 SM_MEM_SIZE + \
			 SM_OBJ_MEM_SIZE)
#define VAL_VSI4_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI4_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN   | VSI_CTL_PWEN    | \
			  VSI_CTL_LLRMW )

#define VAL_VSI5_BS	(VAL_VSI1_BS + \
			 SM_MEM_ADRS + \
			 SM_MEM_SIZE + \
			 SM_OBJ_MEM_SIZE)
#define VAL_VSI5_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#define VAL_VSI5_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI5_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN   | VSI_CTL_PWEN    )

/*
 * VME SLAVE WINDOW FOR A16 SPACE
 *
 * Universe VME A16 Slave window, does not exist.  (Could use window 3.)
 */

#define VME_A16_SLV_BUS		0x0
#define VME_A16_SLV_SIZE	0x0	/* 0, window is disabled */
#define VME_A16_SLV_LOCAL	0x0

/* defines for the UNIV II location monitor register space */

#define VAL_LM_CTL		(LM_CTL_EN | LM_CTL_PGM_BOTH | \
				 LM_CTL_BOTH | LM_CTL_VAS_A32)
#define VAL_LM_BS		(VME_LM_MSTR_BUS + (sysProcNumGet() * \
				 VME_LM_SLV_SIZE))

/* Universe Special Cycle Generator values */

#define	VME_SCG_COMPARE_MASK		0xffffffff
#define VME_SCG_COMPARE_TO_SET		0x00000000
#define VME_SCG_SWAP_TO_SET		0x80000000
#define VME_SCG_COMPARE_TO_CLEAR	0x80000000
#define VME_SCG_SWAP_TO_CLEAR		0x00000000

/* INTERRUPT DEFINES */

#define INT_NUM_IRQ0            	INT_VEC_IRQ0

#define TIMER_INTERRUPT_BASE		0x00
#define EXTERNAL_INTERRUPT_BASE 	0x10
#define INTERNAL_INTERRUPT_BASE		0x20
#define	SERIAL_INTERRUPT_BASE		0x30

/* interrupt Level definitions */

/* EPIC Timers */

/* EPIC timer 0 interrupt level */
#define TIMER0_INT_LVL		( 0x0 + TIMER_INTERRUPT_BASE )

/* EPIC timer 1 interrupt level */
#define TIMER1_INT_LVL		( 0x1 + TIMER_INTERRUPT_BASE )

/* EPIC timer 2 interrupt level */
#define TIMER2_INT_LVL		( 0x2 + TIMER_INTERRUPT_BASE )

/* EPIC timer 3 interrupt level */
#define TIMER3_INT_LVL		( 0x3 + TIMER_INTERRUPT_BASE )

/* External interrupt sources */

/* ethernet interrupt level */
#define LN_INT_LVL		( 0x01 + SERIAL_INTERRUPT_BASE )

/* PC-MIP Type 1 Slot 1 (PMC) */
#define PCMIPT1S1_INT_LVL	( 0x02 + SERIAL_INTERRUPT_BASE )

/* PC-MIP Type 1 Slot 2 */
#define PCMIPT1S2_INT_LVL	( 0x03 + SERIAL_INTERRUPT_BASE )

/* PC-MIP Type 2 Slot 1 */
#define PCMIPT2S1_INT_LVL	( 0x04 + SERIAL_INTERRUPT_BASE )

/* PC-MIP Type 2 Slot 2 */
#define PCMIPT2S2_INT_LVL	( 0x05 + SERIAL_INTERRUPT_BASE )

/* Universe LINT#0 interrupt level ( used for the UNIVERSE chip )*/
#define UNIV_INT_LVL0		( 0x07 + SERIAL_INTERRUPT_BASE )

/* Universe LINT#1 interrupt level */
#define UNIV_INT_LVL1		( 0x08 + SERIAL_INTERRUPT_BASE )

/* Universe LINT#2 interrupt level */
#define UNIV_INT_LVL2		( 0x09 + SERIAL_INTERRUPT_BASE )

/* Universe LINT#3 interrupt level */
#define UNIV_INT_LVL3		( 0x0a + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTA */
#define PCI_INTA_LVL		( 0x07 + SERIAL_INTERRUPT_BASE )

/*  PCI expansion INTB */
#define PCI_INTB_LVL		( 0x08 + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTC */
#define PCI_INTC_LVL		( 0x09 + SERIAL_INTERRUPT_BASE )

/* PCI expansion INTD */
#define PCI_INTD_LVL		( 0x0a + SERIAL_INTERRUPT_BASE )

/* 16550 UART interrupt level (COM port 1) */
#define COM1_INT_LVL		( 0x0d + SERIAL_INTERRUPT_BASE )

/* front panel abort switch */
#define ABORT_INT_LVL		( 0x0e + SERIAL_INTERRUPT_BASE )

/* RTC (watchdog/alarm) */
#define RTC_INT_LVL		( 0x0f + SERIAL_INTERRUPT_BASE )

/* EPIC internal interrupts */

/* Kahlua I2C interrupt */
#define I2C_INT_LVL		(0x00 + INTERNAL_INTERRUPT_BASE )

/* EPIC DMA #0 */
#define DMA0_INT_LVL		(0x01 + INTERNAL_INTERRUPT_BASE )

/* EPIC DMA #1 */
#define DMA1_INT_LVL		(0x02 + INTERNAL_INTERRUPT_BASE )

#define UNIV_INT_LVL		UNIV_INT_LVL0   /* universe int level */

/* interrupt vector definitions */

#define INT_VEC_IRQ0		0x00	/* vector for IRQ0 */

/* MVME2100 interrupt vector definitions */

#define LN_INT_VEC		INT_VEC_IRQ0 + LN_INT_LVL
#define PCMIPT1S1_INT_VEC	INT_VEC_IRQ0 + PCMIPT1S1_INT_LVL
#define PCMIPT1S2_INT_VEC	INT_VEC_IRQ0 + PCMIPT1S2_INT_LVL
#define PCMIPT2S1_INT_VEC	INT_VEC_IRQ0 + PCMIPT2S1_INT_LVL
#define PCMIPT2S2_INT_VEC	INT_VEC_IRQ0 + PCMIPT2S2_INT_LVL
#define UNIV_INT_VEC		INT_VEC_IRQ0 + UNIV_INT_LVL
#define UNIV_INT_VEC1		INT_VEC_IRQ0 + UNIV_INT_LVL1
#define UNIV_INT_VEC2		INT_VEC_IRQ0 + UNIV_INT_LVL2
#define UNIV_INT_VEC3		INT_VEC_IRQ0 + UNIV_INT_LVL3
#define	PCI_INTA_VEC		INT_VEC_IRQ0 + PCI_INTA_LVL
#define	PCI_INTB_VEC		INT_VEC_IRQ0 + PCI_INTB_LVL
#define	PCI_INTC_VEC		INT_VEC_IRQ0 + PCI_INTC_LVL
#define	PCI_INTD_VEC		INT_VEC_IRQ0 + PCI_INTD_LVL
#define COM1_INT_VEC		INT_VEC_IRQ0 + COM1_INT_LVL
#define ABORT_INT_VEC		INT_VEC_IRQ0 + ABORT_INT_LVL
#define RTC_INT_VEC		INT_VEC_IRQ0 + RTC_INT_LVL
#define TIMER0_INT_VEC		INT_VEC_IRQ0 + TIMER0_INT_LVL
#define TIMER1_INT_VEC          INT_VEC_IRQ0 + TIMER1_INT_LVL
#define TIMER2_INT_VEC          INT_VEC_IRQ0 + TIMER2_INT_LVL
#define TIMER3_INT_VEC          INT_VEC_IRQ0 + TIMER3_INT_LVL

/* UNIVERSE chip interrupt vector defines */

#define UNIV_DMA_INT_VEC		0x56	/* DMA interrupt vector */
#define UNIV_VME_SW_IACK_INT_VEC 	0x57	/* VME software IACK vector */
#define UNIV_PCI_SW_INT_VEC		0x58	/* PCI software IACK vector */
#define UNIV_VOWN_INT_VEC		0x59	/* VOWN interrupt vector */
#define UNIV_LERR_INT_VEC		0x5a	/* LErr interrupt vector */
#define UNIV_VERR_INT_VEC		0x5c	/* VErr interrupt vector */
#define UNIV_SYSFAIL_INT_VEC		0x5d	/* SYSFAIL interrupt vector */
#define UNIV_ACFAIL_INT_VEC		0x5f	/* ACFAIL interrupt vector */
#define UNIV_MBOX0_INT_VEC		0x60	/* Mailbox 0 interrupt vector */
#define UNIV_MBOX1_INT_VEC              0x61    /* Mailbox 1 interrupt vector */
#define UNIV_MBOX2_INT_VEC              0x62    /* Mailbox 2 interrupt vector */
#define UNIV_MBOX3_INT_VEC              0x63    /* Mailbox 3 interrupt vector */
#define UNIV_LM0_INT_VEC		0x64	/* Loc. Mon. 0 interrupt vec. */
#define UNIV_LM1_INT_VEC		0x65	/* Loc. Mon. 1 interrupt vec. */
#define UNIV_LM2_INT_VEC		0x66	/* Loc. Mon. 2 interrupt vec. */
#define UNIV_LM3_INT_VEC		0x67	/* Loc. Mon. 3 interrupt vec. */

/*
 * Address range definitions for VME and PCI buses.
 *
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_VME_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)VME_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)VME_MSTR_HI_ADRS))

#define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCI_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_HI_ADRS))

/* PCI bus number for primary PCI bus */

#define PCI_PRIMARY_BUS         0

/* Fixed PMC Span (PCI-to-PCI Bridge) configuration parameters */

#define P2P_CLR_STATUS          0xFFFF0000
#define P2P_SEC_BUS_RESET       (0x0040 << 16)
#define P2P_CLK_ENABLE          0x00       /* enable clocks on all slots */
#define P2P_PMC_DISABLE         0
#define P2P_PMC_ENABLE          7

#ifndef _ASMLANGUAGE

/* PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Structure */

typedef struct pmc_span_parm	/* PMC_SPAN */
    {
    UINT16  parmOffset;		/* offset into configuration header */
    UINT16  parmSize;		/* parmValue size (1, 2 or 4 bytes) */
    UINT32  parmValue;		/* parameter value placed at this offset */
    } PMC_SPAN;

#endif  /* _ASMLANGUAGE */

#define SEC_CLR_STATUS             0xFFFF0000
#define SEC_CACHE_LINE_SIZE        (0x08)
#define SEC_PRIM_LATENCY           0
#define SEC_IO_SPACE_BASE_ADRS     (0x01)
#define SEC_IO_SPACE_LIMIT_ADRS    (0xF1 << 8)
#define SEC_MEM_SPACE_BASE_ADRS    ((PCI_MSTR_MEM_BUS + PMC_SPAN_MEM_BASE) \
				    >> 16)
#define SEC_MEM_SPACE_LIMIT_ADRS   ((PCI_MSTR_MEM_BUS + PMC_SPAN_MEM_BASE + \
				     PMC_SPAN_MEM_SIZE - 1) & 0xFFFF)
#define SEC_MEM_MAP_IO_BASE_ADRS   (0x7F00)
#define SEC_MEM_MAP_IO_LIMIT_ADRS  (0x7000 << 16)
#define	SEC_IO_32SPACE_BASE_ADRS   ((PCI_MSTR_IO_BUS + PMC_SPAN_IO_BASE) >> 16)
#define	SEC_IO_32SPACE_LIMIT_ADRS  ((PCI_MSTR_IO_BUS + PMC_SPAN_IO_BASE + \
				     PMC_SPAN_IO_SIZE - 1) & 0xFFFF)
#define SEC_ISA_BUS                (0x0000 << 16) /* 0 = none, 4 = ISA */
#define SEC_PMC_DISABLE            (0x00)
#define SEC_PMC_ENABLE             (0x07)

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
				     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* INCmv2100h */