📄 mv2100.h
字号:
* memory space as it appears on the PCI bus. */#ifdef CHRP_ADRS_MAP# define PCI_SLV_MEM_SIZE 0x40000000 /* CHRP max is 1 GB */#else /* PReP map */# define PCI_SLV_MEM_SIZE 0x80000000 /* PReP max is 2GB */#endif /* CHRP_ADRS_MAP *//* PCI device select definitions */#define PCI_DEVSEL_PHB 0 /* Kahlua PCI host bridge */#define PCI_DEVSEL_VMEBUS 13 /* Universe II PCI-VMEbus */#define PCI_DEVSEL_ETHERNET 14 /* DEC21143 Ethernet */#define PCI_DEVSEL_PCMIPT1S1 16 /* PC-MIP Type 1 Slot 1 (PMC) */#define PCI_DEVSEL_PCMIPT1S2 17 /* PC-MIP Type 1 Slot 2 */#define PCI_DEVSEL_PCMIPT2S1 18 /* PC-MIP Type 2 Slot 1 */#define PCI_DEVSEL_PCMIPT2S2 19 /* PC-MIP Type 2 Slot 2 *//* * PCI Config Space device addresses based on their device number * * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles */#define CNFG_START_SEARCH 0x5800 /* PCI Space starting offset */#define CNFG_PCI_HOST_BRDG 0x80000000 /* Kahlua PCI host bridge */#define CNFG_IBC_ADRS 0x80005800 /* IBC */#define CNFG_SCSI_ADRS 0x80006000 /* SCSI */#define CNFG_UNIVERSE_ADRS 0x80006800 /* VMEbus Bridge */#define CNFG_LN_ADRS 0x80007000 /* Ethernet Device */#define CNFG_VGA_ADRS 0x80007800 /* Graphics Device */#define CNFG_PCMIPT1S1_ADRS 0x80008000 /* PC-MIP Type 1 Slot 1 (PMC) */#define CNFG_PCMIPT1S2_ADRS 0x80008800 /* PC-MIP Type 1 Slot 2 */#define CNFG_PCMIPT2S1_ADRS 0x80009000 /* PC-MIP Type 2 Slot 1 */#define CNFG_PCMIPT2S2_ADRS 0x80009800 /* PC-MIP Type 2 Slot 2 */ /* Special dec21143 configuration device driver area register */#define PCI_CFG_21143_DA 0x40/* Number of PCI devices */#define NUM_PCI_DEVS 4/* PCI Device/Vendor IDs */#define PCI_ID_UNIVERSE 0x000010e3 /* Id for Universe VME chip */#define PCI_ID_LN_DEC21140 0x00091011 /* Id DEC chip 21140 */#define PCI_ID_LN_DEC21143 0x00191011 /* Id DEC chip 21143 */#define PCI_ID_PRI_LAN PCI_ID_LN_DEC21143 /* Id for Primary LAN */#define PCI_ID_SEC_LAN PCI_ID_LN_DEC21143 /* Id for Secondary LAN */#define PCI_ID_SCSI 0x00031000 /* Id for SYM53C825/75 Chips */#define PCI_ID_SEC_SCSI 0x00011000 /* Id for SYM53C810A Chip */#define PCI_ID_NCR810 0x00011000 /* Id for SYM53C810A Chip */#define PCI_ID_NCR860 0x00061000 /* Id for SYM53C860 Chip */#define PCI_ID_NCR825 0x00031000 /* Id for SYM53C825/75 Chips*/#define PCI_ID_LN_DEC21040 0x00021011 /* Id DEC chip 21040 */#define PCI_ID_5434 0x00a81013 /* Id for CL-GD534 chip */#define PCI_ID_5436 0x00ac1013 /* Id for CL-GD536 chip */#define PCI_ID_BR_DEC21150 0x00221011 /* Id DEC 21150 PCI bridge */#define PCI_ID_KAHLUA_CFG 0x00031057 /* Id for Kahlua config regs *//* PCI to CPU definitions */#ifdef LOCAL_MEM_AUTOSIZE# define DRAM_SIZE ((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)#else# define DRAM_SIZE (LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)#endif /* LOCAL_MEM_AUTOSIZE *//* * Allocate PCI Memory and I/O Space Offsets for PCI devices * * All devices on the primary and secondary busses are allocated 64 kb spaces. * The PMC Span can control up to four PMCs. */#define SCSI_DEV_SPACE 0x10000#define LAN_DEV_SPACE 0x20000#define VGA_DEV_SPACE 0x30000#define PMC_DEV_SPACE 0x40000#define VME_DEV_SPACE 0x50000#define LAN2_DEV_SPACE 0x60000#define SCSI_DEV_SPACE2 0x70000#define SPAN_IO_DEV_SPACE 0x80000#define SPAN_IO_DEV_SIZE 0x40000#define SPAN_MEM_DEV_SPACE 0x02000000#define SPAN_MEM_DEV_SIZE 0x01000000#define SPAN_PREF_DEV_SPACE 0x01000000#define SPAN_PREF_DEV_SIZE 0x01000000/* PCI view of PCI I/O Space for PCI devices */#define PCI_IO_SCSI_ADRS (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE) /* 53C825 */#define PCI_IO_LN_ADRS (PCI_MSTR_IO_BUS + LAN_DEV_SPACE) /* PCnet */#define PCI_IO_VGA_ADRS (PCI_MSTR_IO_BUS + VGA_DEV_SPACE) /* GD5434 */#define PCI_IO_PMC_ADRS (PCI_MSTR_IO_BUS + PMC_DEV_SPACE) /* extra */#define PCI_IO_LN2_ADRS (PCI_MSTR_IO_BUS + LAN2_DEV_SPACE) /* 21040 */#define PCI_IO_SCSI_ADRS2 (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE2) /* 53C825A*//* PCI view of PCI Memory Space for PCI devices */#define PCI_MEM_UNIVERSE_ADRS (PCI_MSTR_MEMIO_BUS + VME_DEV_SPACE)/* Allocated base address of HW devices as seen from CPU */#define SCSI_BASE_ADRS ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE )#define LAN_BASE_ADRS ( PCI_MSTR_IO_LOCAL + LAN_DEV_SPACE )#define LAN2_BASE_ADRS ( PCI_MSTR_IO_LOCAL + LAN2_DEV_SPACE )#define SCSI_BASE_ADRS2 ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE2 )#define UNIVERSE_BASE_ADRS ( PCI_MSTR_MEMIO_LOCAL + VME_DEV_SPACE )/* * System I/O address definitions * * The system resources are mapped into the lower 1MB address * range of FLASH/ROM bank 0 (FFE00000 - FFEFFFFF). */#define MV2100_SIO_BASE 0xFFE00000 /* base address of system I/O */#define MV2100_SIO_SIZE 0x00100000 /* base address of system I/O */#define MV2100_SYS_STAT_REG1 (MV2100_SIO_BASE+0x00000) #define MV2100_SYS_STAT_REG2 (MV2100_SIO_BASE+0x01000)#define MV2100_PCI_PD_REG (MV2100_SIO_BASE+0x02000)#define MV2100_VME_GEO_ADR_REG (MV2100_SIO_BASE+0x03000)#define MV2100_CONFIG_HDR_REG (MV2100_SIO_BASE+0x04000)#define MV2100_COM1_UART (MV2100_SIO_BASE+0x10000)#define MV2100_NVRAM (MV2100_SIO_BASE+0x80000)/* Bit definitions for system status register #1 */#define MV2100_RESET 0x80 /* hard reset of 2100 board */#define MV2100_ABORT 0x10 /* state of the abort signal */#define MV2100_EEPROM_WP 0x08 /* EEPROM write protect bit */#define MV2100_FLASH_WP 0x04 /* INTEL only, FLASH write protect */#define MV2100_FLASH_BSY 0x02 /* AMD only, FLASH device busy */#define MV2100_REF_CLK 0x01 /* reference clock *//* bit definitions for system status register #2 */#define MV2100_BD_FAIL 0x80 /* Board fail indicator */#define MV2100_LED_1 0x40 /* LED 1 bit, for future use */#define MV2100_LED_2 0x20 /* LED 2 bit, for future use */#define MV2100_LED_3 0x10 /* LED 3 bit, for future use */#define MV2100_LED_4 0x08 /* LED 4 bit, for future use *//* * bit definitions for PCI Presence Detect register * ( A cleared condition means a board is present, a set condition * indicates that no board is present ) */#define MV2100_PRSNT8 0x80 /* 0 = PMC carrier board present */#define MV2100_PRSNT7 0x40 /* not used, always 1 */#define MV2100_PRSNT6 0x20 /* not used, always 1 */#define MV2100_PRSNT5 0x10 /* not used, always 1 */#define MV2100_PRSNT4 0x08 /* 0 = PC-MIP type 2 slot 2 board */#define MV2100_PRSNT3 0x04 /* 0 = PC-MIP type 2 slot 1 board */#define MV2100_PRSNT2 0x02 /* 0 = PC-MIP type 1 slot 2 board */#define MV2100_PRSNT1 0x01 /* 0 = PMC or PC-MIP 1 slot 1 board */#define MV2100_PRSNT_MASK 0x8f /* mask bits for PCI Presence reg. *//* * VMEbus Geographical Address register * ( the VMEGA bits may be used to determine which slot in a * VMEbus backplane the board is installed in. The slot number * will be the inverse of the value of the bits read. A value * of 0x1f indicates VME Geographical addressing is not supported ) */#define MV2100_VMEGA 0x1f /* VMEGA bits 3 - 7 */#define MV2100_VMEGAP 0x40 /* VMEbus Geographical Addr parity *//* Configuration Header register bits */#define MV2100_CFG0 0x80 /* 0 = jumper in header position 0 */#define MV2100_CFG1 0x40 /* 0 = jumper in header position 1 */#define MV2100_CFG2 0x20 /* 0 = jumper in header position 2 */#define MV2100_CFG3 0x10 /* 0 = jumper in header position 3 */#define MV2100_CFG4 0x08 /* 0 = jumper in header position 4 */#define MV2100_CFG5 0x04 /* 0 = jumper in header position 5 */#define MV2100_CFG6 0x02 /* 0 = jumper in header position 6 */#define MV2100_CFG7 0x01 /* 0 = jumper in header position 7 */#define BUS_SPEED_MASK 0xF8/* * setup the Base Address for the Kahlua registers, use the 1MB block * just below the VME A16 address space */#ifdef CHRP_ADRS_MAP# define KAHLUA_REGISTERS_BASE (PCI_MSTR_MEM_LOCAL + 0x7cf00000)#else# define KAHLUA_REGISTERS_BASE (PCI_MSTR_MEM_LOCAL + 0x2ee00000)#endif /* CHRP_ADRS_MAP *//* programmable interrupt controller (PIC) */#define PIC_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. *//* programmable interrupt timers */#define PIT_BASE_ADR SL82565_TMR1_CNT0 /* timeraddrs */#define PIT_REG_ADDR_INTERVAL 1#define PIT_CLOCK 1193180/* serial ports (COM1) */#define COM1_BASE_ADR MV2100_COM1_UART /* serial port 1 */#define UART_REG_ADDR_INTERVAL 1 /* addr differential */#define N_UART_CHANNELS 1 /* No. serial I/O chans */#define N_SIO_CHANNELS N_UART_CHANNELS /* No. serial I/O chans *//* * non-volatile (battery-backed) ram defines * the top 16 bytes are used for the RTC registers */#define NVRAM_BASE MV2100_NVRAM /* NVRAM base address */#define BBRAM_ADRS NVRAM_BASE /* base address */#define BBRAM_SIZE 0x1ff0 /* 8k NVRAM Total Size *//* factory ethernet address */#define BB_ENET ((char *)(BBRAM_ADRS + 0x1f2c))/* MK48TXX register settings *//* flag register */#define MK48T_FLAGS ((char *)(BBRAM_ADRS + 0x1ff0))/* alarm clock registers, 4 1byte locations */#define ALARM_CLOCK ((char *)(BBRAM_ADRS + 0x1ff2))/* interrupt register */#define MK48T_INTR ((char *)(BBRAM_ADRS + 0x1ff6))/* watchdog timer register */#define WD_TIMER ((char *)(BBRAM_ADRS + 0x1ff7))/* MK48TXX bb time of day clk, 8 1byte locations */#define TOD_CLOCK ((char *)(BBRAM_ADRS + 0x1ff8))/* m48TXX non volatile ram, RTC and watchdog timer */#define NV_RAM_READ(x) sysNvRead (x)#define NV_RAM_WRITE(x,y) sysNvWrite (x,y)/* ncr810/ncr825 delay loop count */#define NCR810_DELAY_MULT 10/* * UNIVERSE REGISTER SETUP FOR CPU <-> VME MAPPING (via PCI) * * ALL VAL_LSIx and VAL_VSIx values MUST be multiples of 64KB !!! * Except VAL_LSI0 and VAL_VSI0, which must be multiples of 4KB ! *//* * VME MASTER WINDOW FOR UNIV II LM (MAILBOX) REGISTERS * * Universe PCI slave (VME master) window 0 * * Map access to A32 VMEbus (VME LM Regs) (64K) */#define VME_LM_SLV_SIZE 0x00001000 /* this boards reg space 4KB */#define VME_LM_MSTR_SIZE 0x00010000 /* total system reg space 64KB*/#ifndef CHRP_ADRS_MAP /* PReP values *//* * Map access to A32 VMEbus (LM Regs) - 64K MAP FOR PReP vxWorks * This maps: MPU RANGE: 0xf0000000 - 0xf000ffff * to: PCI RANGE: 0x30000000 - 0x3000ffff * to: VME RANGE: 0x40000000 - 0x4000ffff */# define VME_LM_MSTR_LOCAL (PCI_MSTR_MEM_LOCAL + 0x2f000000)# define VME_LM_MSTR_BUS 0x40000000# define VAL_LSI0_BS_VALUE (VME_LM_MSTR_LOCAL - PCI_MSTR_MEMIO_LOCAL)#else /* CHRP values *//* * Map access to A32 VMEbus (LM Regs) - 64K MAP FOR CHRP map vxWorks * This maps: MPU RANGE: 0xf1000000 - 0xf100ffff * to: PCI RANGE: 0xf1000000 - 0xf100ffff * to: VME RANGE: 0xfb000000 - 0xfb00ffff (for legacy compatibility) */# define VME_LM_MSTR_LOCAL (PCI_MSTR_MEM_LOCAL + 0x71000000)# define VME_LM_MSTR_BUS (PCI_MSTR_MEM_BUS + 0x7b000000)# define VAL_LSI0_BS_VALUE VME_LM_MSTR_LOCAL#endif /* CHRP_ADRS_MAP */#define VAL_LSI0_BS (VAL_LSI0_BS_VALUE)#define VAL_LSI0_BD (VAL_LSI0_BS + VME_LM_MSTR_SIZE)#define VAL_LSI0_TO (VME_LM_MSTR_BUS - VAL_LSI0_BS)#define VAL_LSI0_CTL ( LSI_CTL_EN | LSI_CTL_WP |\ LSI_CTL_D64 | LSI_CTL_A32 |\ LSI_CTL_DATA | LSI_CTL_USR |\ LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )/* * VME MASTER WINDOW FOR A32 SPACE * * Universe PCI slave (VME master) window 1 */#ifndef CHRP_ADRS_MAP /* PReP values *//* * Map access to A32 VMEbus - 128M MAP FOR PReP vxWorks * This maps: MPU RANGE: 0xd8000000 - 0xdfffffff * to: PCI RANGE: 0x18000000 - 0x1fffffff * to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE */# define VME_A32_MSTR_LOCAL (PCI_MSTR_MEM_LOCAL + 0x17000000)# define VAL_LSI1_BS_VALUE (VME_A32_MSTR_LOCAL - PCI_MSTR_MEMIO_LOCAL)# if (VME_A32_MSTR_SIZE > 0x08000000)# error VME_A32_MSTR_SIZE cannot exceed 128 MB# endif /* (VME_A32_MSTR_SIZE > 0x08000000) */#else /* CHRP values *//* * Map access to A32 VMEbus - (up to ~1.75GB) MAP FOR CHRP map vxWorks * This maps: MPU RANGE: VME_A32_MSTR_LOCAL - VME_A32_MSTR_LOCAL + * VME_A32_MSTR_SIZE * to: PCI RANGE: VME_A32_MSTR_LOCAL - VME_A32_MSTR_LOCAL + * VME_A32_MSTR_SIZE * to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + * VME_A32_MSTR_SIZE * * NOTE: * - VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE must not exceed * PCI_DYNAMIC_MEM_LOCAL (no overlap of A32 and dynamic PCI memory spaces) * - for local memory sizes greater than 256 MB, set VME_A32_MSTR_LOCAL equal * to the memory size. */# define VME_A32_MSTR_LOCAL PCI_MSTR_MEM_LOCAL# define VAL_LSI1_BS_VALUE (VME_A32_MSTR_LOCAL)#endif /* CHRP_ADRS_MAP */#if ((VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE) > VME_LM_MSTR_BUS) && \ (VME_A32_MSTR_BUS < (VME_LM_MSTR_BUS + VME_LM_MSTR_SIZE))# warning VME A32 space overlaps VME LM/SEM (MAILBOX) REG space#endif /* VME overlap check */#define VAL_LSI1_BS (VAL_LSI1_BS_VALUE)#define VAL_LSI1_BD (VAL_LSI1_BS + VME_A32_MSTR_SIZE)#define VAL_LSI1_TO (VME_A32_MSTR_BUS - VAL_LSI1_BS) /* LSI_CTL_WP | */#define VAL_LSI1_CTL ( LSI_CTL_EN | LSI_CTL_WP |\ LSI_CTL_D64 | LSI_CTL_A32 |\ LSI_CTL_DATA | LSI_CTL_USR |\ LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )/* * VME MASTER WINDOW FOR A24 SPACE * * Universe PCI slave (VME master) window 2 */#ifndef CHRP_ADRS_MAP /* PReP values *//* * Map access to A24 VMEbus - 16M MAP FOR PReP vxWorks * This maps: MPU RANGE: 0xe0000000 - 0xe0ffffff * to: PCI RANGE: 0x20000000 - 0x20ffffff * to: VME RANGE: 0xff000000 - 0xffffffff */# define VME_A24_MSTR_LOCAL (PCI_MSTR_MEM_LOCAL + 0x1f000000)# define VAL_LSI2_BS_VALUE (VME_A24_MSTR_LOCAL - PCI_MSTR_MEMIO_LOCAL)#else /* CHRP values *//* * Map access to A24 VMEbus - 16M MAP FOR CHRP map vxWorks * This maps: MPU RANGE: 0xf0000000 - 0xf0ffffff * to: PCI RANGE: 0xf0000000 - 0xf0ffffff * to: VME RANGE: 0xff000000 - 0xffffffff */# define VME_A24_MSTR_LOCAL (PCI_MSTR_MEM_LOCAL + 0x70000000)# define VAL_LSI2_BS_VALUE (VME_A24_MSTR_LOCAL)# if ((VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE) > VME_A24_MSTR_LOCAL)# error VME A32 space extends into the A24 memory space# endif /* ((VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE) > VME_A24_MSTR_LOCAL) */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -