syslib.c

VxWorks下 Cpv3060的BSP源代码

    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nWords; loopCtr++)
        *bufPtr++ = *(short *)ioAddr;
    }


/*****************************************************************************
*
* sysInWordStringRev - byte reversed word read. 
*
* This function reads a byte reversed word string from a specified io address.
*
* RETURNS: N/A
*/

void sysInWordStringRev
    (
    UINT32      ioAddr,		/* I/O address */
    short *     bufPtr,		/* pointer to data buffer */
    int         nWords		/* number of 2 byte words to read */
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nWords; loopCtr++)
        *bufPtr++ = sysInWordRev(ioAddr);
    }


/*****************************************************************************
*
* sysOutWordString - writes a string of words to an io address.
*
* This function writes a word string from a specified io address.
*
* RETURNS: N/A
*/

void sysOutWordString
    (
    ULONG	ioAddr,		/* I/O address */
    UINT16 *	bufPtr,		/* pointer to data buffer */
    int		nWords		/* number of 2 byte words to write */
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nWords; loopCtr++)
        *(short *)ioAddr = *bufPtr++;
    }


/*****************************************************************************
*
* sysInLongString - reads a string of longwords from an io address.
*
* This function reads a longword string from a specified io address.
*
* RETURNS: N/A
*/

void sysInLongString
    (
    ULONG    ioAddr,		/* I/O address */
    ULONG *  bufPtr,		/* pointer to data buffer */
    int      nLongs		/* number of 4 byte words to read */
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nLongs; loopCtr++)
        *bufPtr++ = *(int *)ioAddr;
    }


/*****************************************************************************
*
* sysOutLongString - writes a string of longwords to an io address.
*
* This function writes a longword string from a specified io address.
*
* RETURNS: N/A
*/

void sysOutLongString
    (
    ULONG	ioAddr,		/* I/O address */
    ULONG *	bufPtr,		/* pointer to data buffer */
    int		nLongs 		/* number of 4 byte words to write */
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nLongs; loopCtr++)
        *(int *)ioAddr = *bufPtr++;
    }


/*****************************************************************************
*
* sysLedUpdate - turn on or off specified LEDs
*
* This function is responsible for turning on or off 1 or more of the
* boards LEDs.  The defines LED_ON and LED_OFF should be used as values
* for the parameter ledAction.
*
* RETURNS: N/A
*/

void sysLedUpdate
    (
    UINT8	ledNumber,	/* LED to turn on/off */
    UINT8	ledAction	/* desired action to perform */
    )
    {
    int		intLevel;

    /* lock out interrupts */

    intLevel = intLock ();

    sysCtlPortState &= 0x0F;
    sysCtlPortState |= (*CTL_PORT & 0xF0);

    /* save the new state of the LEDs */

    if (ledAction == LED_ON)
	sysCtlPortState &= ~(ledNumber);
    else
	sysCtlPortState |= ledNumber;

    /* turn on/off the LED */

    *CTL_PORT = sysCtlPortState;

    /* unlock the interrupts */

    intUnlock (intLevel);
    }


/*****************************************************************************
*
* sysPciInsertLong - Insert field into PCI data long
*
* This function writes a field into a PCI data long without altering any bits
* not present in the field.  It does this by first doing a PCI long read
* (into a temporary location) of the PCI data long which contains the field
* to be altered. It then alters the bits in the temporary location to match
* the desired value of the field.  It then writes back the temporary location
* with a PCI long write.  All PCI accesses are byte and the field to alter is
* specified by the "1" bits in the 'bitMask' parameter.
*
* RETURNS: N/A
*/

void sysPciInsertLong
    (
    UINT32 adrs,         /* PCI address */
    UINT32 bitMask,      /* Mask which defines field to alter */
    UINT32 data          /* data written to the offset */
    )
    {
    UINT32 temp;
    int key;

    key = intLock ();
    temp = sysPciInLong (adrs);
    temp = (temp & ~bitMask) | (data & bitMask);
    sysPciOutLong (adrs, temp);
    intUnlock (key);
    }


/*****************************************************************************
*
* sysPciInsertWord - Insert field into PCI data word
*
* This function writes a field into a PCI data word without altering any bits
* not present in the field.  It does this by first doing a PCI word read
* (into a temporary location) of the PCI data word which contains the field
* to be altered. It then alters the bits in the temporary location to match
* the desired value of the field.  It then writes back the temporary location
* with a PCI word write.  All PCI accesses are word and the field to alter is
* specified by the "1" bits in the 'bitMask' parameter.
*
* RETURNS: N/A
*/

void sysPciInsertWord
    (
    UINT32 adrs,         /* PCI address */
    UINT16 bitMask,      /* Mask which defines field to alter */
    UINT16 data          /* data written to the offset */
    )
    {
    UINT16 temp;
    int key;

    key = intLock ();
    temp = sysPciInWord (adrs);
    temp = (temp & ~bitMask) | (data & bitMask);
    sysPciOutWord (adrs, temp);
    intUnlock (key);
    }


/*****************************************************************************
*
* sysPciInsertByte - Insert field into PCI data byte
*
* This function writes a field into a PCI data byte without altering any bits
* not present in the field.  It does this by first doing a PCI byte read
* (into a temporary location) of the PCI data byte which contains the field
* to be altered. It then alters the bits in the temporary location to match
* the desired value of the field.  It then writes back the temporary location
* with a PCI byte write.  All PCI accesses are byte and the field to alter is
* specified by the "1" bits in the 'bitMask' parameter.
*
* RETURNS: N/A
*/

void sysPciInsertByte
    (
    UINT32 adrs,       /* PCI address */
    UINT8  bitMask,    /* Mask which defines field to alter */
    UINT8  data        /* data written to the offset */
    )
    {
    UINT8 temp;
    int key;

    key = intLock ();
    temp = sysPciInByte (adrs);
    temp = (temp & ~bitMask) | (data & bitMask);
    sysPciOutByte (adrs, temp);
    intUnlock (key);
    }


/*****************************************************************************
*
* sysPciOutByteConfirm - Byte out to PCI memory space and flush buffers.
*
* This function outputs a byte to PCI memory space and then flushes the PCI
* write posting buffers by reading from the target address. Since the PCI
* spec requires the completion of posted writes before the completion of delayed
* reads, when the read completes, the write posting buffers have been flushed.
*
* NOTE: If the write is performed through a PCI-to-PCI bridge to a shared
* location that is subject to unprotected access by multiple simultaneous
* processors, there is the possibility that the bridge will deliver a delayed
* read completion to a PCI bus master which was not the original initiator of
* the delayed read. When this occurs, it appears as if a PCI delayed read had
* passed a posted write, which would violate PCI transaction ordering rules.
* If this is a concern, an additional read must be performed outside of this
* routine to guarantee that the confirming read performed in this routine was
* not aliased.
*
* RETURNS: N/A
*/

void sysPciOutByteConfirm
    (
    UINT32 adrs,       /* PCI address */
    UINT8  data        /* data to be written */
    )
    {
    UINT8 temp;

    sysPciOutByte (adrs, data);
    temp = sysPciInByte (adrs);

    }


/*****************************************************************************
*
* sysPciOutWordConfirm - Word out to PCI memory space and flush buffers.
*
* This function outputs a word to PCI memory space and then flushes the PCI
* write posting buffers by reading from the target address. Since the PCI
* spec requires the completion of posted writes before the completion of delayed
* reads, when the read completes, the write posting buffers have been flushed.
*
* NOTE: If the write is performed through a PCI-to-PCI bridge to a shared
* location that is subject to unprotected access by multiple simultaneous
* processors, there is the possibility that the bridge will deliver a delayed
* read completion to a PCI bus master which was not the original initiator of
* the delayed read. When this occurs, it appears as if a PCI delayed read had
* passed a posted write, which would violate PCI transaction ordering rules.
* If this is a concern, an additional read must be performed outside of this
* routine to guarantee that the confirming read performed in this routine was
* not aliased.
*
* RETURNS: N/A
*/

void sysPciOutWordConfirm
    (
    UINT32 adrs,       /* PCI address */
    UINT16 data        /* data to be written */
    )
    {
    UINT16 temp;

    sysPciOutWord (adrs, data);
    temp = sysPciInWord (adrs);

    }


/*****************************************************************************
*
* sysPciOutLongConfirm - Long word out to PCI memory space and flush buffers.
*
* This function outputs a long word to PCI memory space and then flushes the
* PCI write posting buffers by reading from the target address. Since the PCI
* spec requires the completion of posted writes before the completion of delayed
* reads, when the read completes, the write posting buffers have been flushed.
*
* NOTE: If the write is performed through a PCI-to-PCI bridge to a shared
* location that is subject to unprotected access by multiple simultaneous
* processors, there is the possibility that the bridge will deliver a delayed
* read completion to a PCI bus master which was not the original initiator of
* the delayed read. When this occurs, it appears as if a PCI delayed read had
* passed a posted write, which would violate PCI transaction ordering rules.
* If this is a concern, an additional read must be performed outside of this
* routine to guarantee that the confirming read performed in this routine was
* not aliased.
*
* RETURNS: N/A
*/

void sysPciOutLongConfirm
    (
    UINT32 adrs,       /* PCI address */
    UINT32 data        /* data to be written */
    )
    {
    UINT32 temp;

    sysPciOutLong (adrs, data);
    temp = sysPciInLong (adrs);

    }


/******************************************************************************
*
* sysQspanCapt - capture QSPAN window information
*
* This routine captures the configuration of the QSPAN PPC and PCI slave
* registers. This information is used to perform address translations from
* CPU to PCI addresses and vice versa.
*
* RETURNS: N/A
*
* SEE ALSO: sysBusToLocalAdrs(), sysLocalToBusAdrs()
*/

void sysQspanCapt (void)
    {
    UINT32 index;               /* window counter */
    int immrVal = vxImmrGet();
    UINT32 qspanIndex;
    int	   i;
    UINT32 ba;
    UINT32 bs;
    UINT32 ta;
    UINT32 tav;
    UINT32 size;
    UINT32 mask;
    UINT32 ctlReg;
    UINT32 attReg;
    UINT32 ioBaseAddr;
    UINT32 memBaseAddr;
    UINT32 qspanAddr;

    validQspanWindows = 0;

    index = 0;

    /* setup to do the cpu to pci windows */

    qspanAddr = ((*BR6(immrVal)) & BR_BA_MSK);
    ioBaseAddr = ((*BR5(immrVal)) & BR_BA_MSK);
    memBaseAddr = ioBaseAddr + 0x40000000;

    qspanIndex = QSPAN_QBSI0_CTL;

    /* loop through the 2 QSPAN CPU translation windows */

    for ( i = 0; i < QSPAN_CPU_WIN_CNT; i++)
	{
	QSPAN_READ(qspanAddr + qspanIndex, ctlReg);
	QSPAN_READ(qspanAddr + qspanIndex + 4, attReg);

	/* check for an active window */

	if ( attReg & QSPAN_ENABLE_REG )
	    {
	    validQspanWindows++;
	    bs = ( attReg & QSPAN_QBSI_2GB ) >> 4;
	    ta = (attReg & 0xffff0000);
	    size = qspanSizeTable[bs].blockSize - 1;
	    mask = qspanSizeTable[bs].addrMask;

	    /* check for i/o or mem space */

	    if (ctlReg & QSPAN_QBSI_IO_SPACE)
		{
		tav = (ioBaseAddr & mask) | (ta & ~mask);
		qspanCpuToPciWin[index].winBase = ioBaseAddr;
		qspanCpuToPciWin[index].winLimit = ioBaseAddr + size;
		qspanCpuToPciWin[index].winType = PCI_BAR_SPACE_IO;
		}
	    else
		{
		tav = (memBaseAddr & mask) | (ta & ~mask);
		qspanCpuToPciWin[index].winBase = memBaseAddr;
		qspanCpuToPciWin[index].winLimit = memBaseAddr + size;
		qspanCpuToPciWin[index].winType = PCI_BAR_SPACE_MEM;
		}
	    qspanPciToCpuWin[index].winType = qspanCpuToPciWin[index].winType;
	    qspanPciToCpuWin[index].winBase = tav;
	    qspanPciToCpuWin[index].winLimit = tav + size;
	    }
	qspanIndex += 0x10;
	index++;
	}

    qspanIndex = QSPAN_PBTI0_CTL;

    /* loop through the 2 QSPAN PCI translation windows */

    for ( i = 0; i < QSPAN_PCI_WIN_CNT; i++)
	{
	QSPAN_READ(qspanAddr + qspanIndex, ctlReg);
	QSPAN_READ(qspanAddr + qspanIndex + 4, attReg);

	/* check for an active window */

	if (ctlReg & QSPAN_QBTI_EN)
	    {
	    validQspanWindows++;
	    bs = (ctlReg & QSPAN_QBTI_2GB) >> 24;
	    ba = attReg & 0xffff0000;
	    ta = (attReg & 0x0000ffff) << 16;
	    size = qspanSizeTable[bs].blockSize - 1;
	    mask = qspanSizeTable[bs].addrMask;
	    if (ctlReg & QSPAN_QBTI_IO_SPACE)
		{
		qspanCpuToPciWin[index].winType = PCI_BAR_SPACE_IO;
		qspanPciToCpuWin[index].winT