syslib.c

VxWorks下 Cpv3060的BSP源代码

/* sysLib.c - Motorola CPV3060 board system-dependent library */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1997-2001 Motorola, Inc., All Rights Reserved */
#include "copyright_wrs.h"

/*
modification history
--------------------
02c,21jun02,mil  Update sysSmAnchorFind().  (SPR #76002).
02b,16may02,kab  SPR 71421: Ethernet for MPC860T Rev D3
02a,16sep01,dat  Use of WRS_ASM macro
01z,19mar01,rhk  Add support for QSPAN II chips.
01y,09feb01,rhk  Added reset of FEC into sysFecEnetDisable, removed the
		 call to sysFecEnetDisable from sysHwInit.
01x,06dec00,rhk  Changes made to comply with WRS coding standards.
01w,21nov00,rhk  Updated value store into PDDIR based on processor
		 revision number.
01v,03oct00,rhk  Fixed SBRAM size checking in sysHwInit.
01u,13sep99,rhk  removed CPM ethernet support.
01t,08sep99,rhk  moved the FEC reset from sysFecEnetDisable into the 
		 motFecEnd driver (motFecStop routine).
01s,01sep99,rhk  added SBRAM sizing support in sysHwInit.
01r,31aug99,rhk  added support for motFecEnd driver, added two new routines:
		 sysFecEnetDisable, sysFecEnetEnable.
01q,10aug99,rhk  added support for the standard Motorola VPD interface.
01p,28jul99,srr  made if_fec driver standalone so it is not included here.
01o,14jul99,rhk  code review updates.
01n,12jul99,rhk  changed DEFAULT_SBRAM_SIZE to SBRAM_SIZE in SBRAM page
		 table entry.
01m,09jul99,rhk  added new LED code, battery check code, added Page Table
		 entry for SBRAM, removed legacy 3160 code.
01l,14jun99,srr  replaced old PCI Auto Configuration with WRS version,
                 move page table update for memory autosizing inside define,
                 replaced old method of determining to run PCI Auto Config,
                 changed to support WRS PCI naming conventions.
                 Removed sysPciConfigInsertLong, sysPciConfigInsertWord, &
                 sysPciConfigInsertByte.
		 changed return type of sysIntEnablePIC() from void to STATUS.
                 changed parameter types for sysOutWordString, sysOutLongString
                 sysInWordString, & sysInLongString.
01k,11jun99,srr  Supplemented sysSmParamsCompute with sysSmArg2Compute.
01j,09jun99,srr  changed to support cpv3060.
01i,16dec98,rhk  added interrupt enable/disable support for CPM interrupts.
01h,30nov98,rhk  added Shared Memory support code.
01g,11nov98,rhk  added support routines for Drawbridge PCI-PCI communication.
01f,27oct98,rhk  split the ppc860IntrInit call into 2 calls, one in
		 sysHwInit and one in sysHwInit2 to support PCI
		 interrupt chaining.
01e,27oct98,srr  added support for PCI Auto Configuration.
01d,09oct98,rhk  removed PSP register configurations at end of sysHwInit2.
01c,15sep98,rhk  added routines: sysCtClockCtlrUpdate, sysPldRegUpdate,
		 sysLedUpdate.
01b,14sep98,rhk  moved portion of sysHwInit code into file cpvSystemConfig.c.
01a,27aug98,rhk  ported to CPV3160 from MBX version 01l.
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    ppcDecTimer.c	- PowerPC Decrementer Timer library
    byteNvRam.c		- NVRAM access routines
    cpvI2c.c            - I2C bus access
    qspanPci.c		- QSPAN PCI bus bridge device
    i2cMcp.c          	- I2C micro-chip patch
    if_fec.obj		- Fast Ethernet Controller driver
    pciAutoConfigLib.c  - PCI device auto-configuration library


INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/pci/pciConfigLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"

#include "drv/multi/ppc860Siu.h"
#include "drv/sio/ppc860Sio.h"
#include "sysMotVpdCpv3060.h"
#include "qspanPci.h"		/* QBus-to-PCIBus bridge device */
#include "dec2155xCpci.h"

#include "esf.h"
#include "excLib.h"

#ifdef INCLUDE_SM_NET
#   include "smLib.h"
#   include "smUtilLib.h"
#   include "smPktLib.h"
#   include "smObjLib.h"
#endif  /* INCLUDE_SM_NET */

/* defines */

#define DEFAULT_TAS_CHECKS      10              /* rechecks for soft tas */
#define TAS_CONST               0x80

/* externals */

IMPORT void	i2cMcp();	/* download I2C/SPI RISC microcode patch */
IMPORT void	qspanHostInit(register UINT32 baseAddr);
				/* PIRQ[0:3] route control regs I/O control */
IMPORT void	qspanHostEnable(register UINT32 baseAddr);
IMPORT short	sysInWordRev();
IMPORT int	sysPciErr();
IMPORT int	sysDecGet();
IMPORT int      sysRevNumGet();
IMPORT STATUS	sysPciCfgRead();
IMPORT STATUS	sysPciCfgWrite();
IMPORT int	sysStartType;
IMPORT UINT32	sysQspanId;
IMPORT int	sysQspanRevisionId;
IMPORT void	cpvConfigGlobals();
IMPORT UINT32   sysPciInLong();
IMPORT void	sysPciOutLong();
IMPORT UINT16   sysPciInWord();
IMPORT void     sysPciOutWord();
IMPORT UINT8    sysPciInByte();
IMPORT void	sysPciOutByte();
IMPORT STATUS   sysCpuToPciAdrs (int,  char *, char **);
IMPORT STATUS   sysPciToCpuAdrs (int,  char *, char **);

/* Macro for all i/o operations to use */

#ifndef SYNC
#    define SYNC  WRS_ASM(" sync")
#endif /* SYNC */

#define PCI_HOST_BUS_NBR        0       /* number of bus on far side of  */
					/* Host-PCI bridge */

/* typedefs */

typedef struct qspanWinStruct
    {
    UINT32 winType;   /* mem or i/o */
    UINT32 winBase;   /* start of window */
    UINT32 winLimit;  /* end of window */
    } QSPAN_WIN_STRUCT;

typedef struct qspanWinSize
    {
    UINT32 blockSize;  /* size of PCI window */
    UINT32 addrMask;   /* mask for address translations */
    } QSPAN_WIN_SIZE;

/* globals */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Local DRAM - Must be second entry in sysPhysMemDesc for Auto Sizing */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Burst RAM - Must be the third entry in sysPhysMemDesc for Auto Sizing */

    (void *) SBRAM_BASE,
    (void *) SBRAM_BASE,
    SBRAM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) NV_RAM_BA,
    (void *) NV_RAM_BA,
    NV_RAM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) CSR_BASE_ADDR,
    (void *) CSR_BASE_ADDR,
    CSR_SIZE,				/* 4 k - Board Control and Status */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) INTERNAL_MEM_MAP_ADDR,
    (void *) INTERNAL_MEM_MAP_ADDR,
    INTERNAL_MEM_MAP_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) CPU_PCI_BRIDGE_BA,
    (void *) CPU_PCI_BRIDGE_BA,
    CPU_PCI_BRIDGE_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROM_SIZE,				/* Flash memory */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

QSPAN_WIN_SIZE	qspanSizeTable [] = 
    {
    { 0x00010000, 0x0000ffff },
    { 0x00020000, 0x0001ffff },
    { 0x00040000, 0x0003ffff },
    { 0x00080000, 0x0007ffff },
    { 0x00100000, 0x000fffff },
    { 0x00200000, 0x001fffff },
    { 0x00400000, 0x003fffff },
    { 0x00800000, 0x007fffff },
    { 0x01000000, 0x00ffffff },
    { 0x02000000, 0x01ffffff },
    { 0x04000000, 0x03ffffff },
    { 0x08000000, 0x07ffffff },
    { 0x10000000, 0x0fffffff },
    { 0x20000000, 0x1fffffff },
    { 0x40000000, 0x3fffffff },
    { 0x80000000, 0x7fffffff }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC860) */
char *sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int   sysProcNum;			/* processor number of this CPU */
int   sysFlags;				/* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;		/* by default no VME */
UINT  sysInitStatus = 0;		/* record errors during init */
UINT8 sysCtlPortState;			/* save state of the LEDs */

/* 
 * These globals replace the defines of the same name in cpv3060.h,
 * and should be used after exiting romInit.s.
 */

int   spllMulFactor;			/* SPLL multiplic. factor in PLPRCR*/
int   spllFreq;				/* the system clock rate */
int   brgClkFreq;			/* baud rate generator clock */
int   refreshValue;			/* clock period between DRAM refresh */
int   ptaValue;				/* periodic timer A period */

int   smIntArg1 = -1;                   /* Shared memory SM_INT_ARG1 */
int   smIntArg2 = -1;                   /* Shared memory SM_INT_ARG2 */

QSPAN_WIN_STRUCT qspanCpuToPciWin[QSPAN_WIN_CNT] = { { 0 } };
QSPAN_WIN_STRUCT qspanPciToCpuWin[QSPAN_WIN_CNT] = { { 0 } };
int   validQspanWindows = 0;

/* 
 * XXX set the following array to a unique Ethernet hardware address XXX
 *
 * last 5 nibbles are board specific, initialized in sysHwInit
 */

#ifdef	INCLUDE_MOT_FEC
unsigned char sysFecEnetAddr [6] = {0x08, 0x00, 0x3e, 0x03, 0x02, 0x01};
#endif	/* INCLUDE_MOT_FEC */


/* locals */

LOCAL char sysModelStr[80];

void sysPciTrap (ESFPPC *pEsf);

#ifdef SYS_SM_ANCHOR_POLL_LIST

static SYS_SM_ANCHOR_POLLING_LIST sysSmAnchorPollList[] =
    {
    SYS_SM_ANCHOR_POLL_LIST
    { 0xffffffff, 0xffffffff }  /* Required entry: marks end of list */
    };
#endif /* SYS_SM_ANCHOR_POLL_LIST */

LOCAL int       smUtilTasValue = 0;             /* special soft tas value */

/* forward declarations */

void   		sysClkRateAdjust ( int * );
void            sysPciAutoConfig ();
void		sysDelay( void );
void		sysMsDelay ( UINT );
void    	sysAtaInit( int, int, int );
LOCAL STATUS  	sysCpvIntConnect( VOIDFUNCPTR *, VOIDFUNCPTR, int );
LOCAL int 	sysCpvIntEnable (int);
LOCAL int 	sysCpvIntDisable (int);
void		sysLedUpdate( UINT8, UINT8 );
void		sysPciInsertLong (UINT32, UINT32, UINT32);
void		sysPciInsertWord (UINT32, UINT16, UINT16);
void		sysPciInsertByte (UINT32, UINT8, UINT8);
void    	sysPciOutLongConfirm (UINT32, UINT32);
void    	sysPciOutWordConfirm (UINT32, UINT16);
void    	sysPciOutByteConfirm (UINT32, UINT8);
void		sysQspanCapt (void);
void    	sysDebugMsg(char * str, UINT32  recovery);

#ifdef  INCLUDE_MOT_FEC
STATUS sysFecEnetDisable (UINT32 motCpmaddr);
#endif  /* INCLUDE_MOT_FEC */

#ifdef INCLUDE_SM_NET
    LOCAL STATUS sysPciConfig21554InLong (int, int, int, int, UINT32 *);
    LOCAL STATUS (*cpciConfigInLong)( int, int, int, int, UINT32 *) =
                  sysPciConfig21554InLong;
    LOCAL int sysPciConfigPack21554 ( int, int, int, int);

    LOCAL void   sysSmParamsCompute(void);
    int	sysSmArg2Compute (void);


#   if (SM_OFF_BOARD == TRUE)
#       ifdef SYS_SM_ANCHOR_POLL_LIST
            LOCAL UINT   sysSmAnchorCandidate ( UINT, UINT, UINT);
#       endif /* SYS_SM_ANCHOR_POLL_LIST */
        LOCAL STATUS sysSmAnchorFind ( int, char **);
        LOCAL char   *sysSmAnchorPoll(void);
        char *  sysSmAnchorAdrs();      /* Anchor address (dynamic) */
#   endif /* (SM_OFF_BOARD == TRUE) */
#endif /* INCLUDE_SM_NET */

/* BSP Drivers */

#include "pci/pciConfigLib.c"
#include "pci/pciConfigShow.c"
#include "pci/pciAutoConfigLib.c"
#include "./sysBusPci.c"
#include "sysSerial.c"
#include "ppc860Intr.c"
#include "timer/ppcDecTimer.c"		/* PPC860 & 821 have on chip timers */
#include "mem/byteNvRam.c"		/* NVRAM access routines */
#include "cpvI2c.c"                     /* I2C bus access */
#include "qspanPci.c"                   /* QBus-to-PCIBus bridge device */
#include "sysMotVpdCpv3060.c"
#include "i2cMcp.c"

#if (SERIAL_PORT == SERIAL_PORT_SCC)
#    include "ppc860SioScc.c"
#endif /* (SERIAL_PORT == SERIAL_PORT_SCC) */

#ifdef INCLUDE_DEC2155X
#  include "dec2155xCpci.c"
#endif /* INCLUDE_DEC2155X */

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    sprintf (sysModelStr, "Motorola CPV3060 - PowerPC %s", sysMpuType);
    return (sysModelStr);
    }


/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatanated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/