cpv3060.h

VxWorks下 Cpv3060的BSP源代码

#define CPU2PCI_MSATT_DISABLED  ( CPU2PCI_MSATT_MEM & ~( CPU2PCI_ATTR_REN | \
						         CPU2PCI_ATTR_WEN ) )

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
#   define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
#   define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif /* LOCAL_MEM_AUTOSIZE */

/* PCI device vendor/type identifier definitions */

#define PCI_ID_NCR53C810        0x00011000      /* SCSI, NCR */
#define PCI_ID_NCR53C825        0x00031000      /* SCSI, NCR */
#define PCI_ID_NCR53C875        0x000F1000      /* SCSI, NCR */
#define PCI_ID_AM79C970         0x20001022      /* Ethernet, AMD */
#define PCI_ID_DEC21040         0x00021011      /* Ethernet, DEC */
#define PCI_ID_DEC21140         0x00091011      /* Ethernet, DEC */
#define PCI_ID_GD5430           0x00A01013      /* VGA, Cirrus Logic */
#define PCI_ID_GD5434           0x00A81013      /* VGA, Cirrus Logic */
#define PCI_ID_GD5436           0x00AC1013      /* VGA, Cirrus Logic */
#define PCI_ID_GD5446           0x00B81013      /* VGA, Cirrus Logic */
#define PCI_ID_DIAMOND_PROVIPER 0x9100100E      /* VGA, Diamond */
#define PCI_ID_ATI_MACH64VT     0x56541002      /* VGA, ATI */
#define PCI_ID_MATROX_STORM     0x0519102B      /* VGA, Matrox */
#define PCI_ID_CHIPS_64310      0x00B8102C      /* VGA, CHIPS 64310 */
#define PCI_ID_SL82C105         0x010510AD      /* EIDE, Sonata (Winbond) */
#define PCI_ID_I82378           0x04848086      /* PCI-ISA Bridge, Intel */
#define PCI_ID_W83C553F         0x056510AD      /* PCI-ISA Bridge, Winbond */
#define PCI_ID_QSPAN            0x086010E3      /* QBus-PCI Bridge, Tundra */
#define PCI_ID_QSPAN_II		0x086210E3	/* QSPAN II PCI Bridge chip */
#define PCI_ID_BR_DEC21554      0x00461011      /* Id DEC 21554 PCI bridge */

/* programmable interrupt controller (PIC) */

#define PIC_REG_ADDR_INTERVAL	1	   /* address diff of adjacent regs. */

/* interrupt vector definitions */

#define INT_NUM_IRQ0		0x00	/* intr. number for IRQ0 */
#define INT_VEC_IRQ0		INT_NUM_IRQ0

/* Interrupt Vector/Number to Interrupt Level */

#define	IVEC_TO_ILVL(X)		(UINT) IVEC_TO_INUM(X)
#define	INUM_TO_ILVL(X)		(UINT) (X)

#undef NUM_VEC_MAX
#define NUM_VEC_MAX		115

/* Interrupt Classes */

#define	INT_CLASS_PPC860	0x1
#define	INT_CLASS_RES		0x2
#define	INT_CLASS_CPM		0x3
#define	INT_CLASS_DEC2155X	0x4
#define	INT_CLASS_UNDEF		0x5

/* Interrupt Level to Interrupt Class */

#define INT_CLASS(lev)  	(lev <= 15 ? INT_CLASS_PPC860 :     \
                         	 (lev <= 31 ? INT_CLASS_RES :       \
                          	  (lev <= 63 ? INT_CLASS_CPM :      \
				   (lev <= 95 ? INT_CLASS_UNDEF:    \
				    (lev <= 114 ? INT_CLASS_DEC2155X: \
				     INT_CLASS_UNDEF)))))

/* Interrupt bases  */

#define DEC2155X_INTERRUPT_BASE 	0x60

/* defines for interrupt sources into the SIU */

#define	IV_POWERFAIL		IV_IRQ0	/* Power Fail */
#define IV_NMI			IV_IRQ0	/* non-maskable intr */
#define IV_GROUP		IV_IRQ1	/* group interrupt */
#define	IV_QSPAN		IV_IRQ2	/* QSpan */
#define IV_PMC1_INTC		IV_IRQ3	/* PMC1 Interrupt C */
#define IV_PMC2_INTB		IV_IRQ3	/* PMC2 Interrupt B */
#define IV_QSPAN_PCI		IV_IRQ3	/* QSPAN (PCI) */
#define IV_PMC1_INTB            IV_IRQ4 /* PMC1 Interrupt B */
#define IV_PMC2_INTA            IV_IRQ4 /* PMC2 Interrupt A */
#define IV_PMC1_INTA            IV_IRQ5 /* PMC1 Interrupt A */
#define IV_PMC2_INTD            IV_IRQ5 /* PMC2 Interrupt D */
#define IV_PMC1_INTD		IV_IRQ6	/* PMC1 Interrupt D */
#define IV_PMC2_INTC		IV_IRQ6	/* PMC2 Interrupt C */
#define IV_DEC21554		IV_IRQ6	/* DEC21554 */
#define	IV_ABORT		IV_IRQ7	/* Abort or Stop, this interrupt */
					/* is shared with the MII_TX_CLK */
					/* signal from the FEC, DO NOT USE IT */
         
#define	IV_RTC			IV_LEVEL0	/* Real-Time Clock */
#define	IV_PIT			IV_LEVEL1	/* Periodic Intr Tmr */
#define	IV_TIMEBASE		IV_LEVEL2	/* Timebase Cntr */
				/* IV_LEVEL3: Fast Ethernet Interrupt */
#define	IV_CPM_CTLR		IV_LEVEL4	/* CPM */
#define IV_PIP			IV_LEVEL6	/* Parallel */

/* 
 * Dec2155x (Drawbridge) related defines
 *
 * defines for the DEC2155X interrupts
 *
 * Drawbridge internal interrupt levels
 */

#define DEC2155X_DOORBELL0_INT_LVL      ( 0x00 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL1_INT_LVL      ( 0x01 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL2_INT_LVL      ( 0x02 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL3_INT_LVL      ( 0x03 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL4_INT_LVL      ( 0x04 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL5_INT_LVL      ( 0x05 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL6_INT_LVL      ( 0x06 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL7_INT_LVL      ( 0x07 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL8_INT_LVL      ( 0x08 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL9_INT_LVL      ( 0x09 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL10_INT_LVL     ( 0x0a + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL11_INT_LVL     ( 0x0b + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL12_INT_LVL     ( 0x0c + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL13_INT_LVL     ( 0x0d + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL14_INT_LVL     ( 0x0e + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL15_INT_LVL     ( 0x0f + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PWR_MGMT_INT_LVL       ( 0x10 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_I2O_INT_LVL            ( 0x11 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PG_CRSSNG_INT_LVL      ( 0x12 + DEC2155X_INTERRUPT_BASE )

/* Drawbridge interrupt vectors */

#define DEC2155X_DOORBELL0_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL0_INT_LVL)
#define DEC2155X_DOORBELL1_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL1_INT_LVL)
#define DEC2155X_DOORBELL2_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL2_INT_LVL)
#define DEC2155X_DOORBELL3_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL3_INT_LVL)
#define DEC2155X_DOORBELL4_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL4_INT_LVL)
#define DEC2155X_DOORBELL5_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL5_INT_LVL)
#define DEC2155X_DOORBELL6_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL6_INT_LVL)
#define DEC2155X_DOORBELL7_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL7_INT_LVL)
#define DEC2155X_DOORBELL8_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL8_INT_LVL)
#define DEC2155X_DOORBELL9_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL9_INT_LVL)
#define DEC2155X_DOORBELL10_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL10_INT_LVL)
#define DEC2155X_DOORBELL11_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL11_INT_LVL)
#define DEC2155X_DOORBELL12_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL12_INT_LVL)
#define DEC2155X_DOORBELL13_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL13_INT_LVL)
#define DEC2155X_DOORBELL14_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL14_INT_LVL)
#define DEC2155X_DOORBELL15_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL15_INT_LVL)
#define DEC2155X_PWR_MGMT_INT_VEC   (INT_VEC_IRQ0 + DEC2155X_PWR_MGMT_INT_LVL)
#define DEC2155X_I2O_INT_VEC        (INT_VEC_IRQ0 + DEC2155X_I2O_INT_LVL)
#define DEC2155X_PG_CRSSNG_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_PG_CRSSNG_INT_LVL)

#define DEC2155X_MAILBOX_INT_VEC (DEC2155X_DOORBELL0_INT_VEC + \
                                  DEC2155X_SM_DOORBELL_BIT)

#ifdef INCLUDE_DEC2155X
#   define DEC2155X_BIST_VAL 0x00
#   define DEC2155X_PRI_PRG_IF_VAL 0x00
#   define DEC2155X_PRI_SUBCLASS_VAL 0x20
#   define DEC2155X_PRI_CLASS_VAL 0x0b
#   define DEC2155X_SEC_PRG_IF_VAL 0x00
#   define DEC2155X_SEC_SUBCLASS_VAL 0x80
#   define DEC2155X_SEC_CLASS_VAL 0x06
#   define DEC2155X_MAX_LAT_VAL 0x00
#   define DEC2155X_MIN_GNT_VAL 0xff

#   define DEC2155X_PRI_INT_TO_CPCI_INTA 0x00
#   define DEC2155X_PRI_INT_TO_CPCI_INTB 0x01
#   define DEC2155X_PRI_INT_TO_CPCI_INTC 0x02
#   define DEC2155X_PRI_INT_TO_CPCI_INTD 0x03

#   define DEC2155X_HW_INT_ROUTING_ADRS (ISA_MSTR_IO_LOCAL + 0x832)
#   define DEC2155X_CPCI_HW_INT_ROUTING_VAL DEC2155X_PRI_INT_TO_CPCI_INTA
 
#   define DEC2155X_CHP_CTRL0_VAL 0x0000
#   define DEC2155X_CHP_CTRL1_VAL 0x0000
 
#   define DEC2155X_PRI_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
                                  DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
                                  DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)

#   define DEC2155X_SEC_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
                                  DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
                                  DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
                                  DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)

#endif /* INCLUDE_DEC2155X */

/* CPM UART definitions */

#define TX_BUF_DESC_BA          0x2200
#define RX_BUF_DESC_BA          0x2210
#define TX_BUFFER               0x0300
#define RX_BUFFER               0x0380

/* FEC Register defines for use in sysLib.c */

/* Ethernet Control Register */

#define FEC_ECNTRL(base)        (CAST(VUINT32 *) (base + 0x0E40))

#define FEC_ECNTRL_RESET        0x00000001      /* Ethernet Controller Reset */
#define FEC_ECNTRL_PINMUX       0x00000004      /* select FEC for port D pins */

/* Port A pin definitions */

#define PORT_A_PINS_SER		((1<<3)|(1<<2)) /* serial io, bit 12,13 */

/* Port B pin definitions */

#define PORT_B_PINS_CTL		((1<<14)|(1<<13)|(1<<12)) /* bits 17,18,19 */
#define PORT_B_PINS_SER		((1<<7)|(1<<6)) /* serial io, bits 24,25 */ 
#define PORT_B_PINS_I2C		((1<<5)|(1<<4)) /* I2C, bits 26,27 */

/* Port C pin definitions */

#define PORT_C_PINS_CD		(1<<7)		/* bit 8 */
#define PORT_C_PINS_CTS		(1<<6)   	/* bit 9 */

/* defines for the PCI Configuration Base addresses for MEM and I/O regs. */

#define QSPAN_CFG_BA_MEM        PCI_MSTR_MEM_BUS
#define QSPAN_CTL_PCI_MEM       QSPAN_ENABLE_REG
#define QSPAN_CFG_BA_IO		PCI_MSTR_IO_BUS
#define QSPAN_CTL_PCI_IO        QSPAN_ENABLE_REG

/*
 * define the makeup of the QSPAN PCI Bus Target image 0
 * Base address, Translation address and Control Reg.
 */

#define QSPAN_PBTI_BA_0         PCI_SLV_MEM_BUS
#define QSPAN_PBTI_TA_0         PCI_SLV_MEM_LOCAL
#define QSPAN_PBTI_CTL_REG0     (QSPAN_QBTI_EN | QSPAN_SLV_MEM_SIZE |         \
                                 QSPAN_QBTI_PRT_SIZ32 | QSPAN_QBTI_PWEN | \
                                 QSPAN_QBTI_MEM_SPACE)

/*
 * define the makeup of the QSPAN PCI Bus Target image 1
 * Base address, Translation address and Control Reg.
 */

#define QSPAN_PBTI_BA_1         PCI_SLV_IO_BUS
#define QSPAN_PBTI_TA_1         PCI_SLV_IO_LOCAL
#define QSPAN_PBTI_CTL_REG1     (QSPAN_DISABLE_REG | QSPAN_QBTI_IO_SPACE)

/*
 * Setup the QSPAN Slave Image 0 address translation and control registers.
 *
 * The default values are,
 *  - 32MB PCI I/O space window
 *  - mapped to PCI IO Address 0x00000000 - 0x01ffffff
 *  - no write posting
 *  - image is enabled
 */

#define QSPAN_QBSI_AT_REG0      ((ISA_MSTR_IO_BUS & 0xffff0000) |       \
                                 QSPAN_MSTR_IO_SIZE | QSPAN_QBSI_EN)
#define QSPAN_QBSI_CTL_REG0     (QSPAN_QBSI_IO_SPACE | QSPAN_QBSI_NO_PWEN)

/*
 * Setup the QSPAN Slave Image 1 address translation and control registers.
 *
 * The default values are,
 *  - 32MB PCI MEM space window
 *  - mapped to PCI Memory Address 0x00000000 - 0x01ffffff
 *  - no write posting
 *  - image is enabled
 */

#define QSPAN_QBSI_AT_REG1      ((PCI_MSTR_MEMIO_BUS & 0xffff0000) |      \
                                 QSPAN_MSTR_MEM_SIZE | QSPAN_QBSI_EN)
#define QSPAN_QBSI_CTL_REG1     (QSPAN_QBSI_MEM_SPACE | QSPAN_QBSI_NO_PWEN)


/*
 * PPC860_DPR_I2C assumes two different offsets depending on whether or not
 * the I2C/SPI microcode patch has been applied (no patch -> 0x1c80, patch
 * applied -> 0x1cc0
 *
 * The default macro is defined in drv/sio/ppc860Sio.h.
 */

#undef	PPC860_DPR_I2C
#define PPC860_DPR_I2C(dprbase)                                         \
			((VINT32 *) ((*RCCR(INTERNAL_MEM_MAP_ADDR) & 0x3) ?  \
	 		 (dprbase + 0x1cc0) : (dprbase + 0x1c80) ))

#define PPC860_DPR_I2C_INITIAL(dprbase) ((VINT32 *) (dprbase + 0x1c80))

#define PPC860_I2C_PATCH_INSTALLED                                      \
			((PPC860_DPR_I2C(DPRAM_ADDRESS) !=              \
          		 PPC860_DPR_I2C_INITIAL(DPRAM_ADDRESS)) ? 1:0)

#ifdef SYS_SM_ANCHOR_POLL_LIST
#   ifndef _ASMLANGUAGE
        
        /* Shared memory anchor polling list */

        typedef struct _SYS_SM_ANCHOR_POLLING_LIST
            {
            UINT devVend;
            UINT subIdVend;
            } SYS_SM_ANCHOR_POLLING_LIST;
#   endif /* _ASMLANGUAGE */
#endif /* SYS_SM_ANCHOR_POLL_LIST */

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
				     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )

#ifdef __cplusplus
    }
#endif

#endif /* INCcpv3060h */