cpv3060.h

VxWorks下 Cpv3060的BSP源代码

#define FS_MASK			0xe0000000	/* mask for flash size bits */
#define FS_8MB			0x60000000	/* Soldered flash = 8MB */
#define FS_4MB			0x00000000	/* Soldered flash = 4MB */
#define FS_2MB			0x20000000	/* Soldered flash = 2MB */
#define FS_1MB			0x40000000	/* Soldered flash = 1MB */
#define F_WIDTH			0x10000000	/* 0 = 16 bits, 1 = 32 bits */
#define BAT_BW			0x08000000	/* 0 = low battery, 1 = OK */

#define BAT_CHG			0x08000000	/* 1 = BAT_BW value changed */

#define BAT_IEN			0x08000000	/* 1 = intr enable for */
						/* changes in BAT_BW value */

/* Bit definitions for the Reset Controller Command Register */

#define RCCR_PREFIX		0xf0		/* prefix must be 0b0101 */
#define RCCR_CMD		0x0e		/* command to the reset cntrlr*/
#define RCCR_POSTFIX		0x01		/* 1 = CMD is valid */

/* Bit definitions for the Reset Controller Options Register */

#define RCOR_SW_OPT		0x80		/* Front panel HRESET option */
#define RCOR_QS_OPT		0x40		/* QSPAN RESETO option bit */
#define RCOR_PWR_OPT		0x20		/* power fail option bit */

/* Bit definitions for the Reset Controller Resets Register */

#define RCRR_CON_DIS		0x80		/* console driver enable bit */
#define RCRR_PHY_RST		0x40		/* reset Ethernet PHY bit */
#define RCRR_FL_RST		0x20		/* Main Flash IC reset bit */
#define RCRR_QS_RST		0x10		/* QSPAN reset bit */

/* Bit definitions for the Reset Controller Status Register */

#define RCSR_PWR_RST		0x8000		/* VCC3 and VCC status bit */
#define RCSR_PWR_GD		0x4000		/* system voltage level status*/
#define RCSR_CPCI_RST		0x2000		/* Compact PCI reset status */
#define RCSR_SW_ON		0x1000		/* pushbutton switch status */
#define RCSR_QS_RSTO		0x0800		/* RESETO status of QSPAN */
#define RCSR_SW_OPT		0x0400		/* read back from HRESET opt */
#define RCSR_QS_OPT		0x0200		/* read back of RESETO opt */
#define RCSR_PWR_OPT		0x0100		/* read back of pwr fail opt */
#define RCSR_CMD		0x00e0		/* read back of reset cmnd */
#define RCSR_CON_DIS		0x0008		/* read back of RCRR_CON_DIS */
#define RCSR_PHY_RST		0x0004		/* read back of RCRR_PHY_RST */
#define RCSR_FL_RST		0x0002		/* read back of RCRR_FL_RST */
#define RCSR_QS_RST		0x0001		/* read back of RCRR_QS_RST */



/* PMC BUSMODE Configuration (CMC Capabilities) */

#if (PMC_CNFG_MODE == PMC_CMC_INDEPENDENT)
#   define CTL_PORT_RESET_VALUE	(0)

#elif (PMC_CNFG_MODE == PMC_PCI_PROTOCOL)
#   define CTL_PORT_RESET_VALUE	(CTL_PORT_PM2)

#elif (PMC_CNFG_MODE == PMC_SBUS_PROTOCOL)
#   define CTL_PORT_RESET_VALUE	(CTL_PORT_PM3)

#else
#   define CTL_PORT_RESET_VALUE	(CTL_PORT_PM2)	/* default: PMC_PCI_PROTOCOL */

#endif  /* PMC_CNFG_MODE */

/* defines used for setting/clearing the LEDs */

#define LED_STAT1		CTL_PORT_LED0 /* defines status 1 LED */
#define LED_STAT2		CTL_PORT_LED1 /* defines status 2 LED */
#define LED_STAT3               CTL_PORT_LED2 /* defines status 3 LED */
#define LED_FAULT		CTL_PORT_LED3 /* defines the fault LED */
#define LED_ON			0	 /* command to turn on the LED */
#define LED_OFF			1	 /* command to turn off the LED */

/* CPU type in the PVR */

#define CPU_TYPE_860		0x0050		/* value for PPC860 */
#define	CPU_REV_A1_MASK_NUM	0x0010		/* revision mask num */

/* PHY configuration */

#if (PHY_CNFG_MODE == PHY_CNFG_AUTO_NEGOTIATE)
#   define PHY_CTRL_MODES  PHY_CTRL_AUTO_NEGOTIATE_EN

#elif (PHY_CNFG_MODE == PHY_CNFG_10M_HALF_DUPLEX)
#   define PHY_CTRL_MODES  0

#elif (PHY_CNFG_MODE == PHY_CNFG_10M_FULL_DUPLEX)
#   define PHY_CTRL_MODES  PHY_CTRL_FULL_DUPLEX_EN

#elif (PHY_CNFG_MODE == PHY_CNFG_100M_HALF_DUPLEX)
#   define PHY_CTRL_MODES  PHY_CTRL_100MBPS

#elif (PHY_CNFG_MODE == PHY_CNFG_100M_FULL_DUPLEX)
#   define PHY_CTRL_MODES  (PHY_CTRL_100MBPS | PHY_CTRL_FULL_DUPLEX_EN)

#else
#   define PHY_CTRL_MODES  PHY_CTRL_AUTO_NEGOTIATE_EN      /* default */

#endif  /* PHY_CNFG_MODE */

/* CPV3060 DPRAM addresses */

#define DPRAM_ADDRESS		(INTERNAL_MEM_MAP_ADDR + 0x2000)

#define CPV3060_BD_SIZE		8       /* size of 860 buffer descriptor*/
#define CPV3060_I2C_NUM_BD	2       /* buffer descriptors for I2C */
#define CPV3060_I2C_NUM_BUFFER  32      /* buffers reserved for I2C */

#define DPRAM_I2C_OFFSET        (DPRAM_ADDRESS + 0x0400)
#define DPRAM_I2C_BD            (DPRAM_I2C_OFFSET)
#define DPRAM_I2C_BUFFER        (DPRAM_I2C_OFFSET + \
				 (CPV3060_BD_SIZE * CPV3060_I2C_NUM_BD))

/*
 * The following are used to define space in DPRAM that is only
 * used during system bootup
 */

#define DPRAM_STACK_ALLOC	-0x0200
#define DPRAM_STACK_DEALLOC	0x0200

/* I2C-bus device address definitions */

#define I2C_EEPROM_BANK1_WRITE	0xA4	/* VPD (vital product data) EEPROM */
#define I2C_EEPROM_BANK1_READ	0xA5
#define I2C_EEPROM_BANK2_WRITE	0xA6	/* Bank2 of serial EEPROM */
#define I2C_EEPROM_BANK2_READ	0xA7
#define I2C_DRAM_WRITE		0xA6	/* LRAM (local memory) EEPROM */
#define I2C_DRAM_READ		0xA7
#define I2C_VPD_DATA		I2C_EEPROM_BANK1_WRITE
#define I2C_DRAM_DATA		I2C_EEPROM_BANK2_WRITE

/* RTC register values */

#define RTC_KEY_VALUE		0x55CCAA33

#define DELTA(a,b)             ( abs((int)a - (int)b) )

/* defines for the default configuration values */

#define DEFAULT_CLOCK_SPEED	FREQ_50_MHZ
#define DEFAULT_SDRAM_SIZE	MEM_SIZE_16MB
#define DEFAULT_SBRAM_SIZE	MEM_SIZE_0MB
#define DEFAULT_FLASH_SIZE	MEM_SIZE_1MB
#define DEFAULT_BOOT_TYPE	FLASH_STARTUP
#define DEFAULT_MEM_SPEED	MEM_SPEED_60NS
#define DEFAULT_PROD_IDFR	"CPV3060"
#define DEFAULT_MPU_TYPE	"860T"
#define DEFAULT_NULL_STRING	""
#define DEFAULT_PRODUCT_ID      "Unknown"
#define DEFAULT_PCI_CLOCK       FREQ_33_MHZ

#define SBRAM_SIZE      	DEFAULT_SBRAM_SIZE      /* default is 0 KB */

/* Vital Product Data Support */

#define DPRAM_VPD_BUF_SIZE      0x100
#define VPD_PKT_LIMIT           25      /* Max number of packets expected */
#define VPD_BRD_OFFSET          0       /* offset into board's eeprom for */
					/* vpd data */
#define VPD_MAX_ITEM_SIZE	25

/* Baud Rate Generator division factors */

#define BRG_DIV_BY_1		0
#define BRG_DIV_BY_4		1
#define BRG_DIV_BY_16		2
#define BRG_DIV_BY_64		3

#define BRGCLK_DIV_FACTOR       BRG_DIV_BY_1

/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#define PCI_PRIMARY_CAR	(CPU_PCI_BRIDGE_BA+0x0500) /* PCI config address reg */
#define PCI_PRIMARY_CDR	(CPU_PCI_BRIDGE_BA+0x0504) /* PCI config data    reg */

#ifndef _ASMLANGUAGE

/* PCI I/O function defines */

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)     sysPciConfigInByte (x)
#endif /* PCI_IN_BYTE */
IMPORT  UINT8                 sysPciConfigInByte  (UINT32 address);
#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)     sysPciConfigInWord (x)
#endif /* PCI_IN_WORD */
IMPORT  UINT16                sysPciConfigInWord  (UINT32 address);
#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)     sysPciConfigInLong (x)
#endif /* PCI_IN_LONG */
IMPORT  UINT32                sysPciConfigInLong  (UINT32 address);
#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)  sysPciConfigOutByte (x,y)
#endif /* PCI_OUT_BYTE */
IMPORT  void                  sysPciConfigOutByte (UINT32 address, UINT8 data);
#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)  sysPciConfigOutWord (x,y)
#endif /* PCI_OUT_WORD */
IMPORT  void                  sysPciConfigOutWord (UINT32 address, UINT16 data);
#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)  sysPciConfigOutLong (x,y)
#endif /* PCI_OUT_LONG */
IMPORT  void                  sysPciConfigOutLong (UINT32 address, UINT32 data);
#ifndef PCI_INSERT_LONG
#   define PCI_INSERT_LONG(a,m,d) sysPciInsertLong((a),(m),(d))
    IMPORT  void                  sysPciInsertLong(UINT32 adrs, UINT32 mask, \
                                                   UINT32 data);
#endif /* PCI_INSERT_LONG */
#ifndef PCI_INSERT_WORD
#   define PCI_INSERT_WORD(a,m,d) sysPciInsertWord((a),(m),(d))
    IMPORT  void                  sysPciInsertWord(UINT32 adrs, UINT16 mask, \
                                                   UINT16 data);
#endif /* PCI_INSERT_WORD */
#ifndef PCI_INSERT_BYTE
#   define PCI_INSERT_BYTE(a,m,d) sysPciInsertByte((a),(m),(d))
    IMPORT  void                  sysPciInsertByte(UINT32 adrs, UINT8 mask, \
                                                   UINT8 data);
#endif /* PCI_INSERT_BYTE */

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 8 32-bit value = 64 bytes */

#define PCI_CLINE_SZ		0x8

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/*
 * The following macros define access to PCI and ISA space from the CPU
 * and the base addresses of PCI and ISA spaces on the bus.
 * These macros contain the correct starting addresses and sizes
 * for use in the BSP and user programming.
 */

/* Legacy ISA space size. */

#define ISA_LEGACY_SIZE		0x00004000

/* Access to PCI ISA I/O space */

#define ISA_MSTR_IO_BUS		0x00000000	/* 0 based addressing */
#define ISA_MSTR_IO_SIZE	PTE_ISA_IO_SIZE

/* Access to PCI I/O space */

#define PCI_MSTR_IO_LOCAL	(ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_BUS		(ISA_MSTR_IO_BUS   + ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_SIZE	PTE_PCI_IO_SIZE

/*
 * Access to PCI nonprefetchable memory space (including ISA memory space)
 * Note the size PCI_MSTR_MEMIO_SIZE is defined in config.h
 */

#define PCI_MSTR_MEMIO_LOCAL	(ISA_MSTR_IO_LOCAL + 0x40000000)
#define PCI_MSTR_MEMIO_1MB_OFF	0x00100000	/* Offset:PCI 1MB memory space*/
#define PCI_MSTR_SIZE_MASK	((~(PCI_MSTR_SIZE) + 1) & 0xBFFF8000)

/* Access to PCI memory space (size defined in config.h) */

#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS	(PCI_MSTR_MEMIO_BUS   + PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_SIZE	PTE_PCI_MEM_SIZE

/* PCI Access to local memory space */

#define PCI_SLV_MEM_LOCAL	LOCAL_MEM_LOCAL_ADRS
#define PCI_SLV_MEM_BUS		0x80000000

/* setup the dynamic PCI memory space for PReP */

#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS	/* needed for usrNetwork.c */


/*  There is no I/O space on the MPC bus */

#define PCI_SLV_IO_BUS         0x00000000
#define PCI_SLV_IO_LOCAL       0x00000000
#define PCI_SLV_IO_SIZE        0x00000000
#define PCI_SLV_IO_CODE        0x00000000

/* Base address register defines */

#define PCI_BASEADDR_IO           (1<<0) /* PCI I/O space */
#define PCI_BASEADDR_MEM	  (0<<0) /* PCI Memory space */
#define PCI_BASEADDR_MEM_TYPE     (3<<1) /* memory type mask */
#define PCI_BASEADDR_MEM_32BIT    (0<<1) /* map anywhere in 32-bit addr space */
#define PCI_BASEADDR_MEM_ONEMEG   (1<<1) /* map below 1MB */
#define PCI_BASEADDR_MEM_64BIT    (2<<1) /* map anywhere in 64-bit addr space */
#define PCI_BASEADDR_MEM_PREFETCH (1<<3) /* prefetchable */

/* cmd_reg defines */

#define PCI_CMDREG_IOSP      (1<<0)  /* Enable IO space accesses */
#define PCI_CMDREG_MEMSP     (1<<1)  /* Enable MEM space accesses */
#define PCI_CMDREG_MASTR     (1<<2)  /* Enable PCI Mastership */
#define PCI_CMDREG_SPCYC     (1<<3)  /* Monitor special cycles */
#define PCI_CMDREG_MEMWINV   (1<<4)  /* Enable memory write and invalidate */
#define PCI_CMDREG_VGASNP    (1<<5)  /* Enable VGA palette snooping */
#define PCI_CMDREG_PERR      (1<<6)  /* Enable Parity error response */
#define PCI_CMDREG_STEP      (1<<7)  /* Enable address/data stepping */
#define PCI_CMDREG_SERR      (1<<8)  /* Enable SERR driver */
#define PCI_CMDREG_FSTB2B    (1<<9)  /* Enable back to back transactions */

/* PCI Space Definitions  -- For configuring the RAVEN */

/* PPC Slave Attribute bit definitions */

#define CPU2PCI_ATTR_REN     (1<<7)  /* Read enable */
#define CPU2PCI_ATTR_WEN     (1<<6)  /* Write enable */
#define CPU2PCI_ATTR_WPEN    (1<<4)  /* Write post enable */
#define CPU2PCI_ATTR_MEM     (1<<1)  /* PCI memory cycle */
#define CPU2PCI_ATTR_IOM     (1<<0)  /* PCI I/O mode */

/* CPU to PCI definitions */

#define CPU2PCI_MSATT_MEM	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN | \
				  CPU2PCI_ATTR_MEM )

#define CPU2PCI_MSATT_IO	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN )