cpv3060.h

VxWorks下 Cpv3060的BSP源代码

/* cpv3060.h - Motorola CPV3060 board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1997-2001 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01x,27may02,kab  Add REV_D_4
01w,19mar01,rhk  Added define for QSPAN II chip.
01v,09feb01,rhk  Added defines for FEC Control register and bit settings.
01u,06dec00,rhk  Changes to comply with WRS coding standards.
01t,22nov00,rhk  added revision D.4 define, and defines for PDDIR and 
		 PDDAR initialization.
01s,13sep99,rhk  removed CPM ethernet defines.
01r,09sep99,rhk  removed defines for FEC control register and reset command.
01q,01sep99,rhk  added SBRAM_SIZE define.
01p,31aug99,rhk  changed support from if_fec ethernet driver to the motFecEnd
		 driver.
01o,25aug99,srr  Moved Subsystem ID's to sysMotCpci.h.
01n,09aug99,rhk  removed startup globals in DPRAM.
01m,28jul99,srr  Added support for non-Sitka cPCI boards.
01l,26jul99,rhk  changed placement of qspan registers in PCI I/O space by
		 modifying QSPAN_CFG_BA_IO define.
01k,15jul99,rhk  added defines for SDRAM initialization.
01j,13jul99,rhk  code review changes.
01i,12jul99,rhk  added additonal memory size defines.
01h,16jun99,rhk  changed the board register defines to support 3060.
		 updated the "DEFAULT" defines for cpv.
01h,14jun99,srr  added support for running PCI Auto Config in bootrom only,
                 changed to support WRS PCI naming conventions.
                 changed cache line size from 0x20 to 0x8.
01g,09jun99,srr  changed to support cpv3060.
01f,30nov98,rhk  added support for Shared Memory Interface.
01e,11nov98,rhk  added support for drawbridge, changed PCI_IN_XXX and 
		 PCI_OUT_XXX macros to use sysPciConfigXxxx calls.
01d,02oct98,srr  added support for PCI Auto Configuration.
01c,22sep98,srr  modified define for the FEC interrupt to use IV_LEVEL3.
01b,12sep98,rhk  added/modified defines for the following: mem speed and
		 size, DPRAM globals, VPD, new control/status regs., 
		 default values and LEDs.
01a,27aug98,rhk  ported to CPV3160 from MBX version 01j.
*/

/*
This file contains I/O addresses and related constants for the Motorola
CPV3060 boards.
*/

#ifndef	INCcpv3060h
#define	INCcpv3060h

#ifdef __cplusplus
    extern "C" {
#endif

#include "drv/mem/memDev.h"
#include "ppc860Intr.h"
#include "drv/pcmcia/pccardLib.h"
#include "drv/hdisk/ataDrv.h"
#include "drv/sio/ppc860Sio.h"

#define BUS	0				/* bus-less board */
#define CPU	PPC860				/* CPU type */

/* revision D.4 and greater require special FEC initialization */

#define REV_D_3 0x0501
#define REV_D_4 0x0502

/* Number of TTY definitions */

#undef  NUM_TTY
#define NUM_TTY         	1

/* Number of COM (i8250) channels */

#define N_I8250_CHANNELS        1

/* Console numbers */

#define SMC1_SCC2_NUM		0

/* Serial port Types */

#define SERIAL_PORT_SMC		0
#define SERIAL_PORT_SCC      	1

/* setup values for Port D registers */

#define PDPAR_PORT_BITS		0	/* use Port D as general purpose bits */
#define PDPAR_MII_BITS		0x1fff	/* use Port D in MII mode */
#define PDDIR_PRE_D4_MII	0x1fff  /* select MII bits for pre-D.4 860T */
#define PDDIR_D4_MII		0x1c58	/* for D.4 and newer, must configure */
					/* bits for input (0), or output (1) */

/*
 * Crystal Frequency - This macro defines the input oscillator frequency
 * clocking the PPC860. On the ADS board, the CPU is clocked by a crystal
 * running at 4 Mhz.  For the CPV3060 boards, the frequency should never change
 * from 32KHZ
 */

#define CRYSTAL_FREQ            32768           /* 32.768 Khz */

#define SYS_DELAY		50000		/* loop counter for sysDelay */

#define FREQ_20_MHZ		20000000	/* 20 Mhz */
#define FREQ_25_MHZ		25000000	/* 25 Mhz */
#define FREQ_33_MHZ		33333333	/* 33 Mhz */
#define FREQ_40_MHZ		40000000	/* 40 Mhz */
#define FREQ_50_MHZ		50000000	/* 50 Mhz */
#define FREQ_66_MHZ		66666666	/* 66 Mhz */
#define FREQ_80_MHZ		80000000	/* 80 Mhz */
#define FREQ_100_MHZ		100000000	/* 100 Mhz */

/* 
 * MAX_MPU_SPEED used by mpc860I2cdInit(), it represents a speed which
 * can always be used for reads from I2C bus.  If we ever operate with
 * a higher CPU speed, this constant will have to be adjusted.
 */

#define MAX_MPU_SPEED           60000000

#define MEM_SIZE_0MB		0x0
#define MEM_SIZE_128K           0x00020000
#define MEM_SIZE_256K           0x00040000
#define MEM_SIZE_512K           0x00080000
#define MEM_SIZE_1MB		0x00100000
#define MEM_SIZE_2MB            0x00200000
#define MEM_SIZE_4MB            0x00400000
#define MEM_SIZE_8MB            0x00800000
#define MEM_SIZE_16MB           0x01000000
#define MEM_SIZE_32MB           0x02000000
#define MEM_SIZE_64MB           0x04000000
#define MEM_SIZE_128MB		0x08000000

#define MEM_SPEED_50NS		50
#define MEM_SPEED_60NS		60
#define MEM_SPEED_70NS		70
#define MEM_SPEED_80NS		80
#define MEM_SPEED_90NS		90
#define MAX_MEM_SPEED		MEM_SPEED_90NS

/* SDRAM initialization index values into UPMA table */

#define UPMA_READ_OFFSET	0x05	/* read precharge value */
#define UPMA_WRITE_OFFSET	0x1d	/* write precharge value */
#define UPMA_BURST_WR_OFFSET	0x27	/* generate 8 burst write refreshes */

/* 
 * DRAM refresh frequency - This macro defines the DRAM refresh frequency.
 * i.e.: A DRAM with 1024 rows to refresh in 16ms:
 * DRAM_REFRESH_FREQ = 1024/ 16E-3 = 64E3 hz
 */

#define DRAM_REFRESH_FREQ       64000                   /* 64 kHz */

/* 
 * The dynamic bus clock speed calculation is needed,
 * so PPC_TMR_RATE_SET_ADJUST is defined here and the function
 * sysClkRateAdjust has been added to sysLib.c
 */

#define PPC_TMR_RATE_SET_ADJUST (void) sysClkRateAdjust (&sysDecClkFrequency)

/*
 * SPLL Frequency - gives the SPLL frequency used in romInit.s
 * as a startup value
 */

#define SPLL_FREQ_25MHZ		0x2FB00000

/*
 * The PTP is a register used by the Memory Controller.
 * It divides the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and sends this divided clock to the
 * Periodic Timers, for the UPMA and UPMB.
 */

#define PTP_VALUE		MPTPR_PTP_DIV32
#define PTP_DIVISOR		(64 / (PTP_VALUE >> 8))

/*
 * SPLL_FREQ_REQUESTED - This constant defines the expected system PLL (SPLL)
 * frequency divided by 2.
 */

#define SPLL_FREQ_REQUESTED     FREQ_25_MHZ             /* 25 Mhz */

/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ		SPLL_FREQ_REQUESTED
#define DEC_CLK_TO_INC  	16

/*
 * This macro returns the positive difference between two unsigned ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)  		( abs((int)a - (int)b) )

/* Swap bytes within a 16-bit word */

#define BYTE_SWAP_16(x)         ((LSB(x) << 8) | MSB(x))

/* Translation macro */

#define TRANSLATE(x,y,z)\
	((UINT)(x) - (UINT)(y) + (UINT)(z))

/* clock rates */

#define SYS_CLK_RATE_MIN        1       /* minimum system clock rate */
#define SYS_CLK_RATE_MAX        8000    /* maximum system clock rate */

/* Aux clock rates - not supported in CPV3060, but included for Tornado */

#define AUX_CLK_RATE_MIN	0	/* minimum auxiliary clock rate */
#define AUX_CLK_RATE_MAX	0	/* maximum auxiliary clock rate */

/* define the Base addresses for the CPV3060's MPC860T Memory Map */

#define NV_RAM_BA       	0xFA000000      /* NVRAM base addr */
#define NV_RAM_SIZE     	0x00008000      /* 32KB default for NVRAM */
#define CSR_BASE_ADDR   	0xFA100000      /* CSR base address */
#define CSR_SIZE		0x00001000	/* 4 KB for CSR size */
#define INTERNAL_MEM_MAP_ADDR	0xFA200000	/* IMMR base Address */
#define INTERNAL_MEM_MAP_SIZE	0x00010000	/* 64 K bytes */
#define CPU_PCI_BRIDGE_BA       0xFA210000      /* PCI Bus Bridge base addr */
#define CPU_PCI_BRIDGE_SIZE     0x00010000      /* PCI Bus Bridge size - 64 K */
#define FLASH_P_BA              0xFE000000      /* primary flash base addr */
#define FLASH_S_BA              0xFC000000      /* secondary flash base addr */
#define FLASH_SIZE              0x00800000      /* flash size - 8 MB */
#define SBRAM_BASE		0x0C000000	/* base addr of Burst Ram */

/* BSP configuration error policy */

#define CONTINUE_EXECUTION      0       /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR  1       /* Transfer to System Monitor */

#ifdef NONFATAL_VPD_ERRORS
#    define DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION
#else
#    define DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR
#endif /* NONFATAL_VPD_ERRORS */

/* Memory/Device Base Addresses */

#define QSPAN_BASE_ADRS		CPU_PCI_BRIDGE_BA
#define QSPAN_IACK_REG		0x508
#define QSPAN_DEF_LAT_TIMER	0x0
#define QSPAN_DEF_CACHELINE	QSPAN_MISC0_DISABLE_CACHELINE
#define QSPAN_DEF_BUS_GRANT	QSPAN_SET_S_BG
#define QSPAN_DEF_BG_ACK	QSPAN_SET_S_BB
#define QSPAN_DEF_BYTE_ORDER	QSPAN_BOC_BE	/* use big-endian ordering */
#define QSPAN_DEF_MSTSLV_MODE	QSPAN_MSTSLV_3
#define QSPAN_REVISION_1_0	0x00000000	/* revision 1.0 ID value */
#define QSPAN_REVISION_1_1	0x00000000	/* revision 1.1 ID value */
#define QSPAN_REVISION_1_2	0x00000002	/* revision 1.2 ID value */
#define QSPAN_CPU_WIN_CNT	2
#define QSPAN_PCI_WIN_CNT	2
#define QSPAN_WIN_CNT		(QSPAN_CPU_WIN_CNT + QSPAN_PCI_WIN_CNT)
#define QSPAN_ID_MASK		0x0000ffff	/* select vendor ID only */

/* MPC860 Register Offsets */

#define BASE_REG0_OFFSET	0x0100

/* NVRAM definitions */

#define NV_RAM_USER_AREA 	0x00002000	/* start of NVRAM user area */
#define NV_RAM_ADRS		((char *) NV_RAM_BA)
#define NV_RAM_INTRVL		1

#define BBRAM_SIZE		NV_RAM_SIZE    /* legacy for Validation Tests */

/*
 * The following is the start of user space in NVRAM, the first
 * 256 bytes are used for the boot parameter line
 */

#undef  NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		NV_RAM_USER_AREA

/* Flash memory defines */

#define FLASH_RNGS		FLASH_SIZE	/* maximum size of FLASH mem */

#define MAIN_FLASH_STARTUP	0x0		/* soldered Flash */
#define BOOTROM_STARTUP		0x1		/* sockected Flash */

#define FLASH_MEMORY_WIDTH_8	8
#define FLASH_MEMORY_WIDTH_16	16
#define FLASH_MEMORY_WIDTH_32	32

#define REGISTER_READ		0
#define REGISTER_WRITE		1

/* CPV3060 board control/status register addresses */

#ifdef _ASMLANGUAGE
#   define CTL_PORT		CSR_BASE_ADDR + 0x01	/* PMC config, LEDs */
#else
#   define CTL_PORT		((VINT8 *) (CSR_BASE_ADDR + 0x01)) 
#endif	/* _ASMLANGUAGE */

/* CPV3060 board control/status register definitions */

#define CTL_PORT_PM2            0x80    /* R/W bit for BUSMODE2, PMC */
#define CTL_PORT_PM3            0x40    /* R/W bit for BUSMODE3, PMC */
#define CTL_PORT_PM4            0x20    /* R/W bit for BUSMODE4, PMC */
#define CTL_PORT_RES1           0x10    /* Reserved */
#define CTL_PORT_LED0           0x08    /* LED0 control, 0=ON, 1= OFF */
#define CTL_PORT_LED1           0x04    /* LED1 control, 0=ON, 1= OFF */
#define CTL_PORT_LED2           0x02    /* LED2 control, 0=ON, 1= OFF */
#define CTL_PORT_LED3           0x01    /* LED3 control, 0=ON, 1= OFF */

#define CTL_PORT_P2M1           0x08    /* status of BUSMODE1 from PMC2 */
#define CTL_PORT_P1M1           0x04    /* status of BUSMODE1 from PMC1 */
#define CTL_PORT_TM             0x02    /* Translation module status */
#define CTL_PORT_RES2		0x01	/* Reserved */

/* 
 * Bit definitions for Pseudo board register - these use the PCMCIA
 * registers PIPR, PSCR and PER
 */