rominit.s

VxWorks下 Cpv3060的BSP源代码

	mfspr	r4, IMMR	/* make sure r4 contains IMMR value */
	rlwinm  r4, r4, 0, 0, 15        /* only high 16 bits count */

        /*
         * for the CPV3060 product we need to determine which FLASH
         * memory the reset code is running from, it's either the
         * 8-bit wide socketed type, or the 16/32-bit wide soldered
         * type, this can be determined by examining the port-size
         * bit-field of the "boot" chip select base address register
         */

        lwz     r5, BR0(0) (r4)         /* get the value of BR0 */
        lis     r6, HIADJ(BR_PS_MSK)    /* mask off the Port size bits */
        addi    r6, r6, LO(BR_PS_MSK)
        and     r5, r5, r6
        lis     r6, HIADJ(BR_PS_8)
        addi    r6, r6, LO(BR_PS_8)
        cmpw    r5, r6                  /* check for boot flash execution */
        bne     inSolderedFlash
        lis     r6, HIADJ( cpvMemc50MhzBoot)
        addi    r6, r6, LO(cpvMemc50MhzBoot)
        b       memcRegInit

inSolderedFlash:                /* if we're here, we're in soldered flash */
        lis     r6, HIADJ( cpvMemc50MhzFlash)
        addi    r6, r6, LO(cpvMemc50MhzFlash)

        /*
         * The following block of code is responsible for setting up the
         * BR/OR register pairs which provides up to 8 memory space
         * mappings ( allows access to DRAM, ROM, PCI space and NVRAM ).
         * The BR/OR initialization code will read values out of the
         * requested cpvMemcXXX table and store them in the appropriate
         * Memory Controller Registers.
         */


memcRegInit:

        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)

        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)

        sub     r6, r6, r7              /* subtract romInit base address */
        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */
        or      r11, r4, r4             /* r11 = IMMR */
        ori     r11, r11, BASE_REG0_OFFSET /* point to Base Reg 0 */
        li      r5,  16

memcRegWriteLoop:

        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, 0(r11)             /* store in BR/OR and pt to next reg */
        addi    r11, r11, 4
        addi    r6,  r6,  4
        addi    r5,  r5, -1
        cmpwi   r5,  0
        bne     memcRegWriteLoop

        /* do the MAMR reg. */

        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, 0x170(r4)

        /* do the MBMR reg. */

        lwzu    r10, 4(r6)          /* incr index and get data from table */
        stw     r10, 0x174(r4)

        /* do the MPTPR reg. */

        lwzu    r10, 4(r6)         /* incr index and get data from table */
        sth     r10, 0x17A(r4)

        /* initialize the first 16MB of SDRAM */

	lis	r5, HIADJ(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
			  UPMA_READ_OFFSET)
	addi	r5, r5, LO(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
			   UPMA_READ_OFFSET)
	stw	r5, MCR(0)(r4)
	sync
        lis     r5, HIADJ(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
                          UPMA_BURST_WR_OFFSET)
        addi    r5, r5, LO(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
                           UPMA_BURST_WR_OFFSET)
        stw     r5, MCR(0)(r4)
        sync
	lis     r5, HIADJ(0x00000088)
	addi    r5, r5, LO(0x00000088)
	stw     r5, MAR(0)(r4)
        lis     r5, HIADJ(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
                          UPMA_WRITE_OFFSET)
        addi    r5, r5, LO(MCR_OP_RUN | MCR_MB_CS2 | MCR_MCLF_1X | \
                           UPMA_WRITE_OFFSET)
        stw     r5, MCR(0)(r4)
        sync

	/* enable memory access in BR2 by setting the valid bit */

	lwz	r5, BR2(0)(r4)
	ori	r5, r5, 0x0001
	stw	r5, BR2(0)(r4)
       
        /* Setup the Stack Frame so we can call C routines */

        lis     sp, HIADJ(STACK_ADRS)
        addi    sp, sp, LO(STACK_ADRS)

	/* read and save the VPD information for the board. */

        addi    sp,sp,DPRAM_STACK_ALLOC
        stw     r3, 8(sp)
        bl      sysVpdInit
        lwz     r3, 8(sp)
        addi    sp,sp,DPRAM_STACK_DEALLOC

        /* finish init of SDRAM and do any recalculation of the CS registers */

        addi    sp,sp,DPRAM_STACK_ALLOC
        stw     r3, 8(sp)
        bl      cpvMemcConfig
        lwz     r3, 8(sp)
        addi    sp,sp,DPRAM_STACK_DEALLOC

        /* initialize r2 and r13 according to EABI standard */
#if	FALSE					/* SDA Not supported yet */

	lis	r2, HIADJ(_SDA2_BASE_)
	addi	r2, r2, LO(_SDA2_BASE_)

	lis	r13, HIADJ(_SDA_BASE_)
	addi	r13, r13, LO(_SDA_BASE_)
#endif /* FALSE */

	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)		/* load R6 with C entry point */
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7			/* routine - entry point */
	add	r6, r6, r8 			/* + ROM base */

	mtlr	r6				/* move C entry point to LR */
	blr					/* jump to the C entry point */


/* UPM-A table data ( SDRAMs @ 50MHZ) */

cpvUpma50Mhz:

   /* read single beat cycle */

        .long   0x0EADB804, 0x10BE6004, 0xE0FCC000, 0x11FCD045     /* 00 */
        .long   0xFFFCFC45, 0xEFFCC004, 0x1FFCD044, 0xFFFCF045     /* 04 */


   /* read burst cycle */

        .long   0x0EFDB804, 0x10FE7004, 0xF0FCF080, 0xF0FCF080      /* 08 */
        .long   0xF1FCF045, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 0C */
        .long   0xFFFCF045, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 10 */
        .long   0xFFFCF045, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 14 */


   /* write single beat cycle */

        .long   0x0EADA800, 0x11BE4004, 0xEFFCC004, 0x1FFCD045      /* 18 */
        .long   0xFFFCF045, 0xEFAC0034, 0x1FBC5074, 0xFFFCF045      /* 1C */


   /* write burst cycle */

        .long   0x00FDA800, 0x10FE5000, 0xF0FCF000, 0xF0FCF000      /* 20 */
        .long   0xF1FCF044, 0xFFFCF045, 0xFFFCF045, 0xEFFC3084      /* 24 */
        .long   0x1FFC7044, 0xFFFCF044, 0xFFFCF0C4, 0xFFFCF045      /* 28 */
        .long   0xFFFCF045, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 2C */
  
 
   /* periodic timer expired */
 
        .long   0x1FFC7044, 0xFFFCF044, 0xFFFCF044, 0xFFFCF045      /* 30 */
        .long   0xFFFCF044, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 34 */
        .long   0xFFFCF045, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045      /* 38 */
 
 
   /* exception */
 
        .long   0xFFFCF044, 0xFFFCF045, 0xFFFCF045, 0xFFFCF045       /* 3C */
cpvUpma50MhzEnd:
 
/* Memory Bank table for 50MHz processor running out of bootROM */

cpvMemc50MhzBoot:

/* CS0 - BR0/CR0 (BootROM Memory Array) */

        .long FLASH_P_BA | BR_PS_8 | BR_MS_GPCM | BR_V
        .long (~(FLASH_RNGS)+1) | OR_CSNT_SAM | OR_BI | OR_SCY_4_CLK

/* CS1 - BR1/CR1 (Local SDRAM Memory Array - Bank 1 (optional) ) */

        .long BR_MS_UPMA
        .long OR_ACS_DIV4

/* CS2 - BR2/CR2 (Local SDRAM Memory Array - Bank 2) */

        .long BR_MS_UPMA
        .long (~(LOCAL_MEM_SIZE)+1) | OR_ACS_DIV4

/* CS3 - BR3/CR3 unused */

        .long 0
        .long 0

/* CS4 - BR4/CR4 (NVRAM and Board Control/Status Registers) */

        .long NV_RAM_BA | BR_PS_8 | BR_MS_GPCM | BR_V
        .long (~(0x00200000)+1) | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK

/* CS5 - BR5/CR5 (PCI-Memory and PCI-I/O Space) */

        .long ISA_MSTR_IO_LOCAL | BR_PS_32 | BR_MS_GPCM | BR_V
        .long PCI_MSTR_SIZE_MASK | OR_ACS_DIV1 | OR_BI | OR_SCY_0_CLK | OR_SETA

/* CS6 - BR6/CR6 (PCI-Bus Controller Register Space - QSpan) */

        .long CPU_PCI_BRIDGE_BA | BR_PS_32 | BR_MS_GPCM | BR_V
        .long (~(0x00010000)+1) | OR_ACS_DIV1 | OR_BI | OR_SCY_0_CLK | OR_SETA

/* CS7 - BR7/CR7 (FLASH Memory Array) */

        .long FLASH_S_BA | BR_PS_32 | BR_MS_GPCM | BR_V
        .long (~(FLASH_RNGS)+1) | OR_CSNT_SAM | OR_ACS_DIV1 | \
                OR_BI | OR_SCY_4_CLK

/* MAMR */

        .long 0x18800281

/* MBMR */

        .long 0x0

/* MPTPR */

        .long 0x00000200

/* Memory Bank table for 50MHz processor running out of FLASHROM */

cpvMemc50MhzFlash:

/* CS0 - BR0/CR0 (FLASH Memory Array) */

        .long FLASH_P_BA | BR_PS_32 | BR_MS_GPCM | BR_V
        .long (~(FLASH_RNGS)+1) | OR_CSNT_SAM | OR_ACS_DIV1 | \
                OR_BI | OR_SCY_4_CLK

/* CS1 - BR1/CR1 (Local SDRAM Memory Array - Bank 1 (optional) ) */

        .long BR_MS_UPMA
        .long OR_ACS_DIV4

/* CS2 - BR2/CR2 (Local SDRAM Memory Array - Bank 2) */

        .long BR_MS_UPMA
        .long (~(LOCAL_MEM_SIZE)+1) | OR_ACS_DIV4

/* CS3 - BR3/CR3 unused */

        .long 0
        .long 0

/* CS4 - BR4/CR4 (NVRAM and Board Control/Status Registers) */

        .long NV_RAM_BA | BR_PS_8 | BR_MS_GPCM | BR_V
        .long (~(0x00200000)+1) | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK

/* CS5 - BR5/CR5 (PCI-Memory and PCI-I/O Space) */

        .long ISA_MSTR_IO_LOCAL | BR_PS_32 | BR_MS_GPCM | BR_V
        .long PCI_MSTR_SIZE_MASK | OR_ACS_DIV1 | OR_BI | OR_SCY_0_CLK | OR_SETA

/* CS6 - BR6/CR6 (PCI-Bus Controller Register Space - QSpan) */

        .long CPU_PCI_BRIDGE_BA | BR_PS_32 | BR_MS_GPCM | BR_V
        .long (~(0x00010000)+1) | OR_ACS_DIV1 | OR_BI | OR_SCY_0_CLK | OR_SETA

/* CS7 - BR7/CR7 (BootROM Memory Array) */

        .long FLASH_S_BA | BR_PS_8 | BR_MS_GPCM | BR_V
        .long (~(FLASH_RNGS)+1) | OR_CSNT_SAM | OR_BI | OR_SCY_4_CLK

/* MAMR */

        .long 0x18800281

/* MBMR */

        .long 0x0

/* MPTPR */

        .long 0x00000200