rominit.s

VxWorks下 Cpv3060的BSP源代码

/* romInit.s - Motorola cpv3060 ROM initialization module */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1997-2000 Motorola, Inc. All Rights Reserved */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01i,05dec00,rhk  WRS code standards cleanup.
01h,10aug99,rhk  setup 16MB of SDRAM for use during startup, added call
		 to the standard Motorola VPD initialization routine.
01g,15jul99,srr  make adjustments to cover-up preprocessor warnings.
01f,14jul99,rhk  code review changes, removed setting of SIUMCR_DPC bit
		 in the SIUMCR reg.
01e,09jul99,rhk  eliminated unused UPM and BR/OR tables, eliminated 
		 code to check for multiple CPU speeds.  Added  code
		 to determine which ROM (boot or flash) we are
		 executing in.
01d,14jun99,srr  changed to support WRS PCI naming conventions.
01c,09jun99,srr  changed to support cpv3060.
01b,28oct98,rhk  removed PSP register initialization.
01a,26aug98,rhk  ported from MBX version 01i.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
	
/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
/* externals */

	.extern romStart	/* system initialization routine */
	.extern sysVpdInit
	.extern cpvMemcConfig

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )
*
*/

_romInit:
romInit:
	bl	cold		/* jump to the cold boot initialization */
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1997 Wind River Systems, Inc."
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */

	/*
	 * When the PowerPC 860 is powered on, the processor fletch the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

	lis	r4, HIADJ(start)		/* load r4 with the address */
	addi	r4, r4, LO(start)		/* of start */

	lis	r5, HIADJ(romInit)		/* load r5 with the address */
	addi	r5, r5, LO(romInit)		/* of romInit() */

	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

	sub	r4, r4, r5			/*  */
	add	r4, r4, r6 

	mtspr	LR, r4				/* save destination address*/
						/* into LR register */
	blr					/* jump to flash mem address */
			
start:
	/* clear out r0 */

	xor	r0, r0, r0

	/* set the MSR register to a known state */

	lis	r4, 0x0000		/* enable ME and RI in MSR */
	addi	r4, r4, 0x1002

	mtmsr	r4			/* set MSR */
	mtspr	SRR1,r4			/* set SRR1 the same as MSR */

	/* DER - clear the Debug Enable Register */

	xor	r4, r4, r4		/* clear register R4 */
	mtspr	DER, r4

	/* ICR - clear the Interrupt Cause Register */

	mtspr	ICR, r4

	/* ICTRL - initialize the Instruction Support Control register */

	lis	r5, HIADJ(0x00000007)
	addi	r5, r5, LO(0x00000007)
	mtspr	ICTRL, r5

	/* disable the instruction/data cache */
	
	lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
	addi	r4, r4, LO (CACHE_CMD_DISABLE)
	mtspr	IC_CST, r4				/* disable I cache */
	mtspr	DC_CST, r4				/* disable D cache */

	/* unlock the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
	mtspr	IC_CST, r4			/* unlock all I cache lines */
	mtspr	DC_CST, r4			/* unlock all D cache lines */

	/* invalidate the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_INVALIDATE)    /* load invalidate cmd */
	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
	mtspr	IC_CST, r4		/* invalidate all I cache lines */
	mtspr	DC_CST, r4		/* invalidate all D cache lines */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
	mtspr	IMMR, r4		/* initialize the IMMR register */

	mfspr	r4, IMMR		/* read it back, to be sure */
	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

	/* SYPCR - turn off the system protection stuff */

	/*
	 * There is a preprocessor problem when loading a register with the
	 * most significant bit set.  To work around this, the final value
	 * must be created by adding intermediate values together:
	 *     to get 0x8000, then 0x7000 and 0x1000 would be added;
	 *     to get 0xf000, then 0x7000 and 0x7000 and 0x1000 would be added.
	 *
	 * The following adjustment is NOT good programming practice since
	 * the value of SYPCR_SWTC is what the preprocessor is complaining
	 * about and the definition of SYPCR_SWTC could be changed in the
	 * future making the following code erroneous.
	 */

	lis	r5, HIADJ((SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) \
	                   & 0x7fffffff)
	addis	r5, r5, HIADJ(0x70000000)
	addis	r5, r5, HIADJ(0x10000000)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	stw	r5, SYPCR(0)(r4)

	/* set the SIUMCR register for important debug port, etc... stuff */

	lwz	r5, SIUMCR(0)(r4)
	lis	r6, HIADJ( SIUMCR_DBGC | SIUMCR_FRC | SIUMCR_PNCS | \
			   SIUMCR_MLRC_KR | SIUMCR_SEME)
	addi	r6, r6, LO(SIUMCR_DBGC | SIUMCR_FRC | SIUMCR_PNCS | \
			   SIUMCR_MLRC_KR | SIUMCR_SEME)
	or	r5, r5, r6
	stw	r5, SIUMCR(0)(r4)

	/* TBSCR - initialize the Time Base Status and Control register */

	lis	r5, HIADJ(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
	sth	r5, TBSCR(0)(r4)

	/* unlock the RTC registers */

	lis	r5, HIADJ( RTC_KEY_VALUE )
	addi	r5, r5, LO( RTC_KEY_VALUE )
	stw	r5, RTCSCK(0)(r4)
	stw	r5, RTCK(0)(r4)
	stw	r5, RTSECK(0)(r4)
	stw	r5, RTCALK(0)(r4)

	/* RTCSC - initialize the RTC status and control register */

	lis	r5, HIADJ( RTCSC_SEC | RTCSC_ALR | RTCSC_RTF | RTCSC_RTE )
	addi	r5, r5, LO( RTCSC_SEC | RTCSC_ALR | RTCSC_RTF | RTCSC_RTE )
	sth	r5, RTCSC(0)(r4)

	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)

        /*
         * We used to set the PLPRCR register here to a default value of
         * 25MHz and assume we were operating with a 32768Hz crystal as
         * the primary input clock.  We no longer set it here but in
         * sysHwInit() instead.  In sysHwInit(), we set it with the
         * correct value depending upon both the actual processor speed
         * and the type of clock (32768Hz crystal or 1:1 oscillator).
         * It's important to preserve the MF field of the PLPRCR register
         * in it's "pristine" (out of reset) state until AFTER
         * cpvConfigParamsGet() is called.  cpvConfigParamsGet() queries
         * the MF field and determines which clock, 32KHz crystal (MF
         * field = 511 in this case) or 1:1 oscillator (MF field = 0 in
         * this case) applies.  Clobbering the PLPRCR(MF) field here
         * would destroy the "flag" which allows us to determine the
         * clock type.
	 *
	 * set the SCCR TimeBase = SYSCLK/16 
	 */

	lis	r5, HIADJ( SCCR_TBS)
	addi	r5, r5, LO(SCCR_TBS)
	lwz	r6, SCCR(0)(r4)		/* keep the reset state */
	or	r5, r5,r6		/* OR in the new TimeBase */
	stw	r5, SCCR(0)(r4)

	/* reset the CPM */

	lis	r5, 0x0000		/* load CPM reset command */
	addi	r5, r5,0x7001		/* preprocessor work-around (0x8001) */
	addi	r5, r5,0x1000		/* preprocessor work-around (0x8001) */ 
	sth	r5, CPCR(0)(r4)		/* issue reset command */

	/* divide by 16 */

	li	r5, MPTPR_PTP_DIV32 
	sth	r5, MPTPR(0)(r4)

	lis	r5, HIADJ( (0x0C << MAMR_PTA_SHIFT) | MAMR_PTAE |       \
			  MAMR_DSA_2_CYCL | MAMR_GPL_A4DIS)
	addi	r5, r5, LO((0x0C << MAMR_PTA_SHIFT) | MAMR_PTAE |       \
			   MAMR_DSA_2_CYCL | MAMR_GPL_A4DIS)
	stw	r5, MAMR(0)(r4)

	/*
	 * The following block of code is responsible for programming
	 * the UPMA, which provides the timing for memory accesses.
	 * Load r6/r7 with the start/end address of the UPM table for an
	 * SDRAM running at 50MHZ, as a default.
	 */

	lis	r6, HIADJ( cpvUpma50Mhz)
	addi	r6, r6, LO(cpvUpma50Mhz)

	lis	r7, HIADJ( cpvUpma50MhzEnd)
	addi	r7, r7, LO(cpvUpma50MhzEnd)

	/* 
	 * This portion of the UPMA setup will access the values
	 * from the selected table and store them in UPMA.
	 *
	 * init UPMA for memory access 
	 */

	sub	r5, r7, r6		/* compute table size */
	srawi	r5, r5, 2		/* in integer size */

	/* convert UpmTable to ROM based addressing */

	lis	r7, HIADJ(romInit)	
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* subtract romInit base address */
	add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
	lis	r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
	addi	r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)

upmWriteLoop:	

	/* write the UPM table in the UPM */

	lwz	r10, 0(r6)		/* get data from table */
	stw	r10, MDR(0)(r4)		/* store the data to MD register */

	stw	r9, MCR(0)(r4)		/* issue command to MCR register */

	addi	r6, r6, 4		/* next entry in the table */
	addi	r9, r9, 1		/* next MAD address */
	cmpw	r9, r5			/* done yet ? */
	blt	upmWriteLoop